InES Hardware Abstraction Layer
reg_stm32f4xx.h
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1 /* ----------------------------------------------------------------------------
2  * -- _____ ______ _____ -
3  * -- |_ _| | ____|/ ____| -
4  * -- | | _ __ | |__ | (___ Institute of Embedded Systems -
5  * -- | | | '_ \| __| \___ \ Zurich University of -
6  * -- _| |_| | | | |____ ____) | Applied Sciences -
7  * -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
8  * ------------------------------------------------------------------------- */
15 #ifndef _REG_STM32F4xx_H
16 #define _REG_STM32F4xx_H
17 
18 #include <stdint.h>
19 
20 
21 /* Utilities
22  * ------------------------------------------------------------------------- */
23 
24 /* Set and clear bit in register. */
25 #define REG_SET(REG, BIT) ( (REG) |= (BIT) )
26 #define REG_CLR(REG, BIT) ( (REG) &= ~(BIT) )
27 
28 /* Toggle (set, then clear) bit in register */
29 #define REG_TGL(REG, BIT) do { \
30  REG_SET((REG), (BIT)); \
31  REG_CLR((REG), (BIT)); \
32  } while(0)
33 
34 
35 /* RCC - register clock control
36  * ------------------------------------------------------------------------- */
37 
44 typedef struct {
45  volatile uint32_t CR;
46  volatile uint32_t PLLCFGR;
47  volatile uint32_t CFGR;
48  volatile uint32_t CIR;
49  volatile uint32_t AHB1RSTR;
50  volatile uint32_t AHB2RSTR;
51  volatile uint32_t AHB3RSTR;
52  uint32_t RESERVED;
53  volatile uint32_t APB1RSTR;
54  volatile uint32_t APB2RSTR;
55  uint32_t RESERVED1[2];
56  volatile uint32_t AHB1ENR;
57  volatile uint32_t AHB2ENR;
58  volatile uint32_t AHB3ENR;
59  uint32_t RESERVED2;
60  volatile uint32_t APB1ENR;
61  volatile uint32_t APB2ENR;
62  uint32_t RESERVED3[2];
63  volatile uint32_t AHB1LPENR;
64  volatile uint32_t AHB2LPENR;
65  volatile uint32_t AHB3LPENR;
66  uint32_t RESERVED4;
67  volatile uint32_t APB1LPENR;
68  volatile uint32_t APB2LPENR;
69  uint32_t RESERVED5[2];
70  volatile uint32_t BDCR;
71  volatile uint32_t CSR;
72  uint32_t RESERVED6[2];
73  volatile uint32_t SSCGR;
74  volatile uint32_t PLLI2SCFGR;
75  volatile uint32_t PLLSAICFGR;
76  volatile uint32_t DCKCFGR;
77 } reg_rcc_t;
78 
79 
80 #ifdef TESTING
81  extern reg_rcc_t rcc_testing;
82  #define RCC ( (reg_rcc_t *) &rcc_testing )
83 #else
84  #define RCC ( (reg_rcc_t *) 0x40023800 )
85 #endif
86 
87 
88 /* FLASH - flash interface register
89  * ------------------------------------------------------------------------- */
90 
97 typedef struct {
98  volatile uint32_t ACR;
99  volatile uint32_t KEYR;
100  volatile uint32_t OPTKEYR;
101  volatile uint32_t SR;
102  volatile uint32_t CR;
103  volatile uint32_t OPTCR;
104  volatile uint32_t OPTCR1;
105 } reg_flash_t;
106 
107 
108 #ifdef TESTING
109  extern reg_flash_t flash_testing;
110  #define FLASH ( (reg_flash_t *) &flash_testing )
111 #else
112  #define FLASH ( (reg_flash_t *) 0x40023c00 )
113 #endif
114 
115 /* CRC - checksum calculation unit
116  * ------------------------------------------------------------------------- */
117 
124 typedef struct {
125  volatile uint32_t DR;
126  volatile uint32_t IDR;
127  volatile uint32_t CR;
128 } reg_crc_t;
129 
130 
131 /* Register macro */
132 
133 #ifdef TESTING
134  extern reg_crc_t crc_testing;
135  #define CRC ( (reg_crc_t *) &crc_testing )
136 #else
137  #define CRC ( (reg_crc_t *) 0x40023000 )
138 #endif
139 
140 
141 /* Helper macros */
142 
143 #define CRC_RCC_PATTERN ( 0x1 << 12u )
144 #define CRC_RESET() REG_TGL(RCC->AHB1RSTR, CRC_RCC_PATTERN)
145 #define CRC_ENABLE() REG_SET(RCC->AHB1ENR, CRC_RCC_PATTERN)
146 #define CRC_DISABLE() REG_CLR(RCC->AHB1ENR, CRC_RCC_PATTERN)
147 #define CRC_LP_ENABLE() REG_SET(RCC->AHB1LPENR, CRC_RCC_PATTERN)
148 #define CRC_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, CRC_RCC_PATTERN)
149 
150 
151 /* PWR - power controller
152  * ------------------------------------------------------------------------- */
153 
160 typedef struct {
161  volatile uint32_t CR;
162  volatile uint32_t CSR;
163 } reg_pwr_t;
164 
165 
166 /* Register macro */
167 
168 #ifdef TESTING
169  extern reg_pwr_t pwr_testing;
170  #define PWR ( (reg_pwr_t *) &pwr_testing )
171 #else
172  #define PWR ( (reg_pwr_t *) 0x40007000 )
173 #endif
174 
175 /* Helper macros */
176 
177 #define PWR_RCC_PATTERN ( 0x1 << 28u )
178 #define PWR_RESET() REG_TGL(RCC->APB1RSTR, PWR_RCC_PATTERN)
179 #define PWR_ENABLE() REG_SET(RCC->APB1ENR, PWR_RCC_PATTERN)
180 #define PWR_DISABLE() REG_CLR(RCC->APB1ENR, PWR_RCC_PATTERN)
181 #define PWR_LP_ENABLE() REG_SET(RCC->APB1LPENR, PWR_RCC_PATTERN)
182 #define PWR_LP_DISABLE() REG_CLR(RCC->APB1LPENR, PWR_RCC_PATTERN)
183 
184 
185 /* GPIO - general purpose input / output
186  * ------------------------------------------------------------------------- */
187 
194 typedef struct {
195  volatile uint32_t MODER;
196  volatile uint32_t OTYPER;
197  volatile uint32_t OSPEEDR;
198  volatile uint32_t PUPDR;
199  volatile uint32_t IDR;
200  volatile uint32_t ODR;
201  volatile uint32_t BSRR;
202  volatile uint32_t LCKR;
203  volatile uint32_t AFRL;
204  volatile uint32_t AFRH;
205 } reg_gpio_t;
206 
207 
208 /* Register macros */
209 
210 
211 #ifdef TESTING
212  extern reg_gpio_t gpioa_testing;
213  extern reg_gpio_t gpiob_testing;
214  extern reg_gpio_t gpioc_testing;
215  extern reg_gpio_t gpiod_testing;
216  extern reg_gpio_t gpioe_testing;
217  extern reg_gpio_t gpiof_testing;
218  extern reg_gpio_t gpiog_testing;
219  extern reg_gpio_t gpioh_testing;
220  extern reg_gpio_t gpioi_testing;
221  extern reg_gpio_t gpioj_testing;
222  extern reg_gpio_t gpiok_testing;
223  #define GPIOA ( (reg_gpio_t *) &gpioa_testing )
224  #define GPIOB ( (reg_gpio_t *) &gpiob_testing )
225  #define GPIOC ( (reg_gpio_t *) &gpioc_testing )
226  #define GPIOD ( (reg_gpio_t *) &gpiod_testing )
227  #define GPIOE ( (reg_gpio_t *) &gpioe_testing )
228  #define GPIOF ( (reg_gpio_t *) &gpiof_testing )
229  #define GPIOG ( (reg_gpio_t *) &gpiog_testing )
230  #define GPIOH ( (reg_gpio_t *) &gpioh_testing )
231  #define GPIOI ( (reg_gpio_t *) &gpioi_testing )
232  #define GPIOJ ( (reg_gpio_t *) &gpioj_testing )
233  #define GPIOK ( (reg_gpio_t *) &gpiok_testing )
234 #else
235  #define GPIOA ( (reg_gpio_t *) 0x40020000 )
236  #define GPIOB ( (reg_gpio_t *) 0x40020400 )
237  #define GPIOC ( (reg_gpio_t *) 0x40020800 )
238  #define GPIOD ( (reg_gpio_t *) 0x40020c00 )
239  #define GPIOE ( (reg_gpio_t *) 0x40021000 )
240  #define GPIOF ( (reg_gpio_t *) 0x40021400 )
241  #define GPIOG ( (reg_gpio_t *) 0x40021800 )
242  #define GPIOH ( (reg_gpio_t *) 0x40021c00 )
243  #define GPIOI ( (reg_gpio_t *) 0x40022000 )
244  #define GPIOJ ( (reg_gpio_t *) 0x40022400 )
245  #define GPIOK ( (reg_gpio_t *) 0x40022800 )
246 #endif
247 
248 
249 /* Helper macros */
250 
251 #define GPIOA_RCC_PATTERN ( 0x1 << 0u )
252 #define GPIOA_RESET() REG_TGL(RCC->AHB1RSTR, GPIOA_RCC_PATTERN)
253 #define GPIOA_ENABLE() REG_SET(RCC->AHB1ENR, GPIOA_RCC_PATTERN)
254 #define GPIOA_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOA_RCC_PATTERN)
255 #define GPIOA_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOA_RCC_PATTERN)
256 #define GPIOA_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOA_RCC_PATTERN)
257 
258 #define GPIOB_RCC_PATTERN ( 0x1 << 1u )
259 #define GPIOB_RESET() REG_TGL(RCC->AHB1RSTR, GPIOB_RCC_PATTERN)
260 #define GPIOB_ENABLE() REG_SET(RCC->AHB1ENR, GPIOB_RCC_PATTERN)
261 #define GPIOB_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOB_RCC_PATTERN)
262 #define GPIOB_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOB_RCC_PATTERN)
263 #define GPIOB_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOB_RCC_PATTERN)
264 
265 #define GPIOC_RCC_PATTERN ( 0x1 << 2u )
266 #define GPIOC_RESET() REG_TGL(RCC->AHB1RSTR, GPIOC_RCC_PATTERN)
267 #define GPIOC_ENABLE() REG_SET(RCC->AHB1ENR, GPIOC_RCC_PATTERN)
268 #define GPIOC_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOC_RCC_PATTERN)
269 #define GPIOC_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOC_RCC_PATTERN)
270 #define GPIOC_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOC_RCC_PATTERN)
271 
272 #define GPIOD_RCC_PATTERN ( 0x1 << 3u )
273 #define GPIOD_RESET() REG_TGL(RCC->AHB1RSTR, GPIOD_RCC_PATTERN)
274 #define GPIOD_ENABLE() REG_SET(RCC->AHB1ENR, GPIOD_RCC_PATTERN)
275 #define GPIOD_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOD_RCC_PATTERN)
276 #define GPIOD_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOD_RCC_PATTERN)
277 #define GPIOD_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOD_RCC_PATTERN)
278 
279 #define GPIOE_RCC_PATTERN ( 0x1 << 4u )
280 #define GPIOE_RESET() REG_TGL(RCC->AHB1RSTR, GPIOE_RCC_PATTERN)
281 #define GPIOE_ENABLE() REG_SET(RCC->AHB1ENR, GPIOE_RCC_PATTERN)
282 #define GPIOE_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOE_RCC_PATTERN)
283 #define GPIOE_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOE_RCC_PATTERN)
284 #define GPIOE_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOE_RCC_PATTERN)
285 
286 #define GPIOF_RCC_PATTERN ( 0x1 << 5u )
287 #define GPIOF_RESET() REG_TGL(RCC->AHB1RSTR, GPIOF_RCC_PATTERN)
288 #define GPIOF_ENABLE() REG_SET(RCC->AHB1ENR, GPIOF_RCC_PATTERN)
289 #define GPIOF_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOF_RCC_PATTERN)
290 #define GPIOF_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOF_RCC_PATTERN)
291 #define GPIOF_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOF_RCC_PATTERN)
292 
293 #define GPIOG_RCC_PATTERN ( 0x1 << 6u )
294 #define GPIOG_RESET() REG_TGL(RCC->AHB1RSTR, GPIOG_RCC_PATTERN)
295 #define GPIOG_ENABLE() REG_SET(RCC->AHB1ENR, GPIOG_RCC_PATTERN)
296 #define GPIOG_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOG_RCC_PATTERN)
297 #define GPIOG_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOG_RCC_PATTERN)
298 #define GPIOG_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOG_RCC_PATTERN)
299 
300 #define GPIOH_RCC_PATTERN ( 0x1 << 7u )
301 #define GPIOH_RESET() REG_TGL(RCC->AHB1RSTR, GPIOH_RCC_PATTERN)
302 #define GPIOH_ENABLE() REG_SET(RCC->AHB1ENR, GPIOH_RCC_PATTERN)
303 #define GPIOH_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOH_RCC_PATTERN)
304 #define GPIOH_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOH_RCC_PATTERN)
305 #define GPIOH_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOH_RCC_PATTERN)
306 
307 #define GPIOI_RCC_PATTERN ( 0x1 << 8u )
308 #define GPIOI_RESET() REG_TGL(RCC->AHB1RSTR, GPIOI_RCC_PATTERN)
309 #define GPIOI_ENABLE() REG_SET(RCC->AHB1ENR, GPIOI_RCC_PATTERN)
310 #define GPIOI_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOI_RCC_PATTERN)
311 #define GPIOI_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOI_RCC_PATTERN)
312 #define GPIOI_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOI_RCC_PATTERN)
313 
314 #define GPIOJ_RCC_PATTERN ( 0x1 << 9u )
315 #define GPIOJ_RESET() REG_TGL(RCC->AHB1RSTR, GPIOJ_RCC_PATTERN)
316 #define GPIOJ_ENABLE() REG_SET(RCC->AHB1ENR, GPIOJ_RCC_PATTERN)
317 #define GPIOJ_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOJ_RCC_PATTERN)
318 #define GPIOJ_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOJ_RCC_PATTERN)
319 #define GPIOJ_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOJ_RCC_PATTERN)
320 
321 #define GPIOK_RCC_PATTERN ( 0x1 << 10u )
322 #define GPIOK_RESET() REG_TGL(RCC->AHB1RSTR, GPIOK_RCC_PATTERN)
323 #define GPIOK_ENABLE() REG_SET(RCC->AHB1ENR, GPIOK_RCC_PATTERN)
324 #define GPIOK_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOK_RCC_PATTERN)
325 #define GPIOK_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOK_RCC_PATTERN)
326 #define GPIOK_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOK_RCC_PATTERN)
327 
328 
329 /* SYSCFG - system configuration controller
330  * ------------------------------------------------------------------------- */
331 
338 typedef struct {
339  volatile uint32_t MEMRMP;
340  volatile uint32_t PMC;
341  volatile uint32_t EXTICR1;
342  volatile uint32_t EXTICR2;
343  volatile uint32_t EXTICR3;
344  volatile uint32_t EXTICR4;
345  uint32_t RESERVED[2];
346  volatile uint32_t CMPCR;
347 } reg_syscfg_t;
348 
349 
350 /* Register macro */
351 
352 #ifdef TESTING
353  extern reg_syscfg_t syscfg_testing;
354  #define SYSCFG ( (reg_syscfg_t *) &syscfg_testing )
355 #else
356  #define SYSCFG ( (reg_syscfg_t *) 0x40013800 )
357 #endif
358 
359 
360 /* Helper macros */
361 
362 #define SYSCFG_RCC_PATTERN ( 0x1 << 14u )
363 #define SYSCFG_RESET() REG_TGL(RCC->APB2RSTR, SYSCFG_RCC_PATTERN)
364 #define SYSCFG_ENABLE() REG_SET(RCC->APB2ENR, SYSCFG_RCC_PATTERN)
365 #define SYSCFG_DISABLE() REG_CLR(RCC->APB2ENR, SYSCFG_RCC_PATTERN)
366 #define SYSCFG_LP_ENABLE() REG_SET(RCC->APB2LPENR, SYSCFG_RCC_PATTERN)
367 #define SYSCFG_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SYSCFG_RCC_PATTERN)
368 
369 
370 /* DMA - direct memory access
371  * ------------------------------------------------------------------------- */
372 
377 typedef struct {
378  volatile uint32_t CR;
379  volatile uint32_t NDTR;
380  volatile uint32_t PAR;
381  volatile uint32_t M0AR;
382  volatile uint32_t M1AR;
383  volatile uint32_t FCR;
384 } reg_dma_stream_t;
385 
386 
393 typedef struct {
394  volatile uint32_t LISR;
395  volatile uint32_t HISR;
396  volatile uint32_t LIFCR;
397  volatile uint32_t HIFCR;
398  reg_dma_stream_t STREAM[8];
399 } reg_dma_t;
400 
401 
402 /* Register macros */
403 
404 #ifdef TESTING
405  extern reg_dma_t dma1_testing;
406  extern reg_dma_t dma2_testing;
407  #define DMA1 ( (reg_dma_t *) &dma1_testing )
408  #define DMA2 ( (reg_dma_t *) &dma2_testing )
409 #else
410  #define DMA1 ( (reg_dma_t *) 0x40026000 )
411  #define DMA2 ( (reg_dma_t *) 0x40026400 )
412 #endif
413 
414 
415 /* Helper macros */
416 
417 #define DMA1_RCC_PATTERN ( 0x1 << 21u )
418 #define DMA1_RESET() REG_TGL(RCC->AHB1RSTR, DMA1_RCC_PATTERN)
419 #define DMA1_ENABLE() REG_SET(RCC->AHB1ENR, DMA1_RCC_PATTERN)
420 #define DMA1_DISABLE() REG_CLR(RCC->AHB1ENR, DMA1_RCC_PATTERN)
421 #define DMA1_LP_ENABLE() REG_SET(RCC->AHB1LPENR, DMA1_RCC_PATTERN)
422 #define DMA1_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, DMA1_RCC_PATTERN)
423 
424 #define DMA2_RCC_PATTERN ( 0x1 << 22u )
425 #define DMA2_RESET() REG_TGL(RCC->AHB1RSTR, DMA2_RCC_PATTERN)
426 #define DMA2_ENABLE() REG_SET(RCC->AHB1ENR, DMA2_RCC_PATTERN)
427 #define DMA2_DISABLE() REG_CLR(RCC->AHB1ENR, DMA2_RCC_PATTERN)
428 #define DMA2_LP_ENABLE() REG_SET(RCC->AHB1LPENR, DMA2_RCC_PATTERN)
429 #define DMA2_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, DMA2_RCC_PATTERN)
430 
431 
432 /* DMA2D - direct memory access
433  * ------------------------------------------------------------------------- */
434 
439 typedef struct {
440  volatile uint32_t CR;
441  volatile uint32_t ISR;
442  volatile uint32_t IFCR;
443  volatile uint32_t FGMAR;
444  volatile uint32_t FGOR;
445  volatile uint32_t BGMAR;
446  volatile uint32_t BGOR;
447  volatile uint32_t FGPFCCR;
448  volatile uint32_t FGCOLR;
449  volatile uint32_t BGPFCCR;
450  volatile uint32_t BGCOLR;
451  volatile uint32_t FGCMAR;
452  volatile uint32_t BGCMAR;
453  volatile uint32_t OPFCCR;
454  volatile uint32_t OCOLR;
455  volatile uint32_t OMAR;
456  volatile uint32_t OOR;
457  volatile uint32_t NLR;
458  volatile uint32_t LWR;
459  volatile uint32_t AMTCR;
460 } reg_dma2d_t;
461 
462 
463 /* Register macros */
464 
465 #ifdef TESTING
466  extern reg_dma2d_t dma2d_testing;
467  #define DMA2D ( (reg_dma2d_t *) &dma2d_testing )
468 #else
469  #define DMA2D ( (reg_dma2d_t *) 0x4002b000 )
470 #endif
471 
472 
473 /* Helper macros */
474 
475 #define DMA2D_RCC_PATTERN ( 0x1 << 23u )
476 #define DMA2D_RESET() REG_TGL(RCC->AHB1RSTR, DMA1_RCC_PATTERN)
477 #define DMA2D_ENABLE() REG_SET(RCC->AHB1ENR, DMA1_RCC_PATTERN)
478 #define DMA2D_DISABLE() REG_CLR(RCC->AHB1ENR, DMA1_RCC_PATTERN)
479 #define DMA2D_LP_ENABLE() REG_SET(RCC->AHB1LPENR, DMA1_RCC_PATTERN)
480 #define DMA2D_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, DMA1_RCC_PATTERN)
481 
482 
483 /* NVIC - nested vector interrupt controller
484  * ------------------------------------------------------------------------- */
485 
492 typedef struct {
493  volatile uint32_t ISER0;
494  volatile uint32_t ISER1;
495  volatile uint32_t ISER2;
496  uint32_t RESERVED1[29];
497  volatile uint32_t ICER0;
498  volatile uint32_t ICER1;
499  volatile uint32_t ICER2;
500  uint32_t RESERVED2[29];
501  volatile uint32_t ISPR0;
502  volatile uint32_t ISPR1;
503  volatile uint32_t ISPR2;
504  uint32_t RESERVED3[29];
505  volatile uint32_t ICPR0;
506  volatile uint32_t ICPR1;
507  volatile uint32_t ICPR2;
508  uint32_t RESERVED4[29];
509  volatile uint32_t IABR0;
510  volatile uint32_t IABR1;
511  volatile uint32_t IABR2;
512  uint32_t RESERVED5[61];
513  volatile uint8_t IP[81];
514  uint8_t RESERVED6[3];
515  uint32_t RESERVED7[684];
516  volatile uint32_t STIR;
517 } reg_nvic_t;
518 
519 
520 /* Register macro */
521 
522 #ifdef TESTING
523  extern reg_nvic_t nvic_testing;
524  #define NVIC ( (reg_nvic_t *) &nvic_testing )
525 #else
526  #define NVIC ( (reg_nvic_t *) 0xe000e100 )
527 #endif
528 
529 /* EXTI - external interrupt
530  * ------------------------------------------------------------------------- */
531 
538 typedef struct {
539  volatile uint32_t IMR;
540  volatile uint32_t EMR;
541  volatile uint32_t RTSR;
542  volatile uint32_t FTSR;
543  volatile uint32_t SWIER;
544  volatile uint32_t PR;
545 } reg_exti_t;
546 
547 
548 /* Register macro */
549 
550 #ifdef TESTING
551  extern reg_exti_t exti_testing;
552  #define EXTI ( (reg_exti_t *) &exti_testing )
553 #else
554  #define EXTI ( (reg_exti_t *) 0x40013c00 )
555 #endif
556 
557 
558 /* ADC - analog digital converter
559  * ------------------------------------------------------------------------- */
560 
567 typedef struct {
568  volatile uint32_t SR;
569  volatile uint32_t CR1;
570  volatile uint32_t CR2;
571  volatile uint32_t SMPR1;
572  volatile uint32_t SMPR2;
573  volatile uint32_t JOFR1;
574  volatile uint32_t JOFR2;
575  volatile uint32_t JOFR3;
576  volatile uint32_t JOFR4;
577  volatile uint32_t HTR;
578  volatile uint32_t LTR;
579  volatile uint32_t SQR1;
580  volatile uint32_t SQR2;
581  volatile uint32_t SQR3;
582  volatile uint32_t JSQR;
583  volatile uint32_t JDR1;
584  volatile uint32_t JDR2;
585  volatile uint32_t JDR3;
586  volatile uint32_t JDR4;
587  volatile uint32_t DR;
588 } reg_adc_t;
589 
590 
591 /* Register macros */
592 
593 #ifdef TESTING
594  extern reg_adc_t adc1_testing;
595  extern reg_adc_t adc2_testing;
596  extern reg_adc_t adc3_testing;
597  #define ADC1 ( (reg_adc_t *) &adc1_testing )
598  #define ADC2 ( (reg_adc_t *) &adc2_testing )
599  #define ADC3 ( (reg_adc_t *) &adc3_testing )
600 #else
601  #define ADC1 ( (reg_adc_t *) 0x40012000 )
602  #define ADC2 ( (reg_adc_t *) 0x40012100 )
603  #define ADC3 ( (reg_adc_t *) 0x40012200 )
604 #endif
605 
606 
607 /* Helper macros */
608 
609 #define ADC1_RCC_PATTERN ( 0x1 << 8u )
610 #define ADC1_ENABLE() REG_SET(RCC->APB2ENR, ADC1_RCC_PATTERN)
611 #define ADC1_DISABLE() REG_CLR(RCC->APB2ENR, ADC1_RCC_PATTERN)
612 #define ADC1_LP_ENABLE() REG_SET(RCC->APB2LPENR, ADC1_RCC_PATTERN)
613 #define ADC1_LP_DISABLE() REG_CLR(RCC->APB2LPENR, ADC1_RCC_PATTERN)
614 
615 #define ADC2_RCC_PATTERN ( 0x1 << 9u )
616 #define ADC2_ENABLE() REG_SET(RCC->APB2ENR, ADC2_RCC_PATTERN)
617 #define ADC2_DISABLE() REG_CLR(RCC->APB2ENR, ADC2_RCC_PATTERN)
618 #define ADC2_LP_ENABLE() REG_SET(RCC->APB2LPENR, ADC2_RCC_PATTERN)
619 #define ADC2_LP_DISABLE() REG_CLR(RCC->APB2LPENR, ADC2_RCC_PATTERN)
620 
621 #define ADC3_RCC_PATTERN ( 0x1 << 10u )
622 #define ADC3_ENABLE() REG_SET(RCC->APB2ENR, ADC3_RCC_PATTERN)
623 #define ADC3_DISABLE() REG_CLR(RCC->APB2ENR, ADC3_RCC_PATTERN)
624 #define ADC3_LP_ENABLE() REG_SET(RCC->APB2LPENR, ADC3_RCC_PATTERN)
625 #define ADC3_LP_DISABLE() REG_CLR(RCC->APB2LPENR, ADC3_RCC_PATTERN)
626 
627 #define ADCx_RESET() REG_TGL(RCC->APB2RSTR, ADC1_RCC_PATTERN)
628 
629 
636 typedef struct {
637  volatile uint32_t CSR;
638  volatile uint32_t CCR;
639  volatile uint32_t CDR;
640 } reg_adccom_t;
641 
642 
643 /* Register macro */
644 
645 #ifdef TESTING
646  extern reg_adccom_t adccom_testing;
647  #define ADCCOM ( (reg_adccom_t *) &adccom_testing )
648 #else
649  #define ADCCOM ( (reg_adccom_t *) 0x40012300 )
650 #endif
651 
652 
653 /* DAC - digital analog converter
654  * ------------------------------------------------------------------------- */
655 
662 typedef struct {
663  volatile uint32_t CR;
664  volatile uint32_t SWTRIGR;
665  volatile uint32_t DHR12R1;
666  volatile uint32_t DHR12L1;
667  volatile uint32_t DHR8R1;
668  volatile uint32_t DHR12R2;
669  volatile uint32_t DHR12L2;
670  volatile uint32_t DHR8R2;
671  volatile uint32_t DHR12RD;
672  volatile uint32_t DHR12LD;
673  volatile uint32_t DHR8RD;
674  volatile uint32_t DOR1;
675  volatile uint32_t DOR2;
676  volatile uint32_t SR;
677 } reg_dac_t;
678 
679 
680 /* Register macro */
681 
682 #ifdef TESTING
683  extern reg_dac_t dac_testing;
684  #define DAC ( (reg_dac_t *) &dac_testing )
685 #else
686  #define DAC ( (reg_dac_t *) 0x40007400 )
687 #endif
688 
689 
690 /* Helper macros */
691 
692 #define DAC_RCC_PATTERN ( 0x1 << 29u )
693 #define DAC_RESET() REG_TGL(RCC->APB1RSTR, DAC_RCC_PATTERN)
694 #define DAC_ENABLE() REG_SET(RCC->APB1ENR, DAC_RCC_PATTERN)
695 #define DAC_DISABLE() REG_CLR(RCC->APB1ENR, DAC_RCC_PATTERN)
696 #define DAC_LP_ENABLE() REG_SET(RCC->APB1LPENR, DAC_RCC_PATTERN)
697 #define DAC_LP_DISABLE() REG_CLR(RCC->APB1LPENR, DAC_RCC_PATTERN)
698 
699 
700 /* DCMI - digital camery mxxx interface
701  * ------------------------------------------------------------------------- */
702 
709 typedef struct {
710  volatile uint32_t CR;
711  volatile uint32_t SR;
712  volatile uint32_t RIS;
713  volatile uint32_t IER;
714  volatile uint32_t MIS;
715  volatile uint32_t ICR;
716  volatile uint32_t ESCR;
717  volatile uint32_t ESUR;
718  volatile uint32_t CWSTRT;
719  volatile uint32_t CWSIZE;
720  volatile uint32_t DR;
721 } reg_dcmi_t;
722 
723 
724 /* Register macro */
725 
726 #ifdef TESTING
727  extern reg_dcmi_t dcmi_testing;
728  #define DCMI ( (reg_dcmi_t *) &dcmi_testing )
729 #else
730  #define DCMI ( (reg_dcmi_t *) 0x50050000 )
731 #endif
732 
733 
734 /* Helper macros */
735 
736 #define DCMI_RCC_PATTERN ( 0x1 << 0u )
737 #define DCMI_RESET() REG_TGL(RCC->AHB2RSTR, DCMI_RCC_PATTERN)
738 #define DCMI_ENABLE() REG_SET(RCC->AHB2ENR, DCMI_RCC_PATTERN)
739 #define DCMI_DISABLE() REG_CLR(RCC->AHB2ENR, DCMI_RCC_PATTERN)
740 #define DCMI_LP_ENABLE() REG_SET(RCC->AHB2LPENR, DCMI_RCC_PATTERN)
741 #define DCMI_LP_DISABLE() REG_CLR(RCC->AHB2LPENR, DCMI_RCC_PATTERN)
742 
743 
744 /* LTDC - liquid txxx display controller
745  * ------------------------------------------------------------------------- */
746 
751 typedef struct {
752  volatile uint32_t CR;
753  volatile uint32_t WHPCR;
754  volatile uint32_t WVPCR;
755  volatile uint32_t CKCR;
756  volatile uint32_t PFCR;
757  volatile uint32_t CACR;
758  volatile uint32_t DCCR;
759  volatile uint32_t BFCR;
760  volatile uint32_t CFBAR;
761  volatile uint32_t CFBLR;
762  volatile uint32_t CFBLNR;
763  volatile uint32_t CLUTWR;
764 } reg_ltdc_lc_t;
765 
766 
773 typedef struct {
774  uint32_t RESERVED1[2];
775  volatile uint32_t SSCR;
776  volatile uint32_t BPCR;
777  volatile uint32_t AWCR;
778  volatile uint32_t TWCR;
779  volatile uint32_t GCR;
780  volatile uint32_t SRCR;
781  volatile uint32_t BCCR;
782  volatile uint32_t IER;
783  volatile uint32_t ISR;
784  volatile uint32_t ICR;
785  volatile uint32_t LIPCR;
786  volatile uint32_t CPSR;
787  volatile uint32_t CDSR;
788  uint32_t RESERVED2[14];
789  reg_ltdc_lc_t LAYER1;
790  uint32_t RESERVED3[15];
791  reg_ltdc_lc_t LAYER2;
792 } reg_ltdc_t;
793 
794 
795 /* Register macro */
796 
797 #ifdef TESTING
798  extern reg_ltdc_t ltdc_testing;
799  #define LTDC ( (reg_ltdc_t *) &ltdc_testing )
800 #else
801  #define LTDC ( (reg_ltdc_t *) 0x40016800 )
802 #endif
803 
804 
805 /* Helper macros */
806 
807 #define LTDC_RCC_PATTERN ( 0x1 << 26u )
808 #define LTDC_RESET() REG_TGL(RCC->APB2RSTR, LTDC_RCC_PATTERN)
809 #define LTDC_ENABLE() REG_SET(RCC->APB2ENR, LTDC_RCC_PATTERN)
810 #define LTDC_DISABLE() REG_CLR(RCC->APB2ENR, LTDC_RCC_PATTERN)
811 #define LTDC_LP_ENABLE() REG_SET(RCC->APB2LPENR, LTDC_RCC_PATTERN)
812 #define LTDC_LP_DISABLE() REG_CLR(RCC->APB2LPENR, LTDC_RCC_PATTERN)
813 
814 
815 /* TIM - timer
816  * ------------------------------------------------------------------------- */
817 
824 typedef struct {
825  volatile uint32_t CR1;
826  volatile uint32_t CR2;
827  volatile uint32_t SMCR;
828  volatile uint32_t DIER;
829  volatile uint32_t SR;
830  volatile uint32_t EGR;
831  volatile uint32_t CCMR1;
832  volatile uint32_t CCMR2;
833  volatile uint32_t CCER;
834  volatile uint32_t CNT;
835  volatile uint32_t PSC;
836  volatile uint32_t ARR;
837  volatile uint32_t RCR;
838  volatile uint32_t CCR1;
839  volatile uint32_t CCR2;
840  volatile uint32_t CCR3;
841  volatile uint32_t CCR4;
842  volatile uint32_t BDTR;
843  volatile uint32_t DCR;
844  volatile uint32_t DMAR;
845  volatile uint32_t OR;
846 } reg_tim_t;
847 
848 
849 /* Register macros */
850 
851 
852 #ifdef TESTING
853  extern reg_tim_t tim1_testing;
854  extern reg_tim_t tim2_testing;
855  extern reg_tim_t tim3_testing;
856  extern reg_tim_t tim4_testing;
857  extern reg_tim_t tim5_testing;
858  extern reg_tim_t tim6_testing;
859  extern reg_tim_t tim7_testing;
860  extern reg_tim_t tim8_testing;
861  extern reg_tim_t tim9_testing;
862  extern reg_tim_t tim10_testing;
863  extern reg_tim_t tim11_testing;
864  extern reg_tim_t tim12_testing;
865  extern reg_tim_t tim13_testing;
866  extern reg_tim_t tim14_testing;
867  #define TIM1 ( (reg_tim_t *) &tim1_testing )
868  #define TIM2 ( (reg_tim_t *) &tim2_testing )
869  #define TIM3 ( (reg_tim_t *) &tim3_testing )
870  #define TIM4 ( (reg_tim_t *) &tim4_testing )
871  #define TIM5 ( (reg_tim_t *) &tim5_testing )
872  #define TIM6 ( (reg_tim_t *) &tim6_testing )
873  #define TIM7 ( (reg_tim_t *) &tim7_testing )
874  #define TIM8 ( (reg_tim_t *) &tim8_testing )
875  #define TIM9 ( (reg_tim_t *) &tim9_testing )
876  #define TIM10 ( (reg_tim_t *) &tim10_testing )
877  #define TIM11 ( (reg_tim_t *) &tim11_testing )
878  #define TIM12 ( (reg_tim_t *) &tim12_testing )
879  #define TIM13 ( (reg_tim_t *) &tim13_testing )
880  #define TIM14 ( (reg_tim_t *) &tim14_testing )
881 #else
882  #define TIM1 ( (reg_tim_t *) 0x40010000 )
883  #define TIM2 ( (reg_tim_t *) 0x40000000 )
884  #define TIM3 ( (reg_tim_t *) 0x40000400 )
885  #define TIM4 ( (reg_tim_t *) 0x40000800 )
886  #define TIM5 ( (reg_tim_t *) 0x40000c00 )
887  #define TIM6 ( (reg_tim_t *) 0x40001000 )
888  #define TIM7 ( (reg_tim_t *) 0x40001400 )
889  #define TIM8 ( (reg_tim_t *) 0x40010400 )
890  #define TIM9 ( (reg_tim_t *) 0x40014000 )
891  #define TIM10 ( (reg_tim_t *) 0x40014400 )
892  #define TIM11 ( (reg_tim_t *) 0x40014800 )
893  #define TIM12 ( (reg_tim_t *) 0x40001800 )
894  #define TIM13 ( (reg_tim_t *) 0x40001c00 )
895  #define TIM14 ( (reg_tim_t *) 0x40002000 )
896 #endif
897 
898 
899 /* Helper macros */
900 
901 #define TIM1_RCC_PATTERN ( 0x1 << 0u )
902 #define TIM1_RESET() REG_TGL(RCC->APB2RSTR, TIM1_RCC_PATTERN)
903 #define TIM1_ENABLE() REG_SET(RCC->APB2ENR, TIM1_RCC_PATTERN)
904 #define TIM1_DISABLE() REG_CLR(RCC->APB2ENR, TIM1_RCC_PATTERN)
905 #define TIM1_LP_ENABLE() REG_SET(RCC->APB2LPENR, TIM1_RCC_PATTERN)
906 #define TIM1_LP_DISABLE() REG_CLR(RCC->APB2LPENR, TIM1_RCC_PATTERN)
907 
908 #define TIM2_RCC_PATTERN ( 0x1 << 0u )
909 #define TIM2_RESET() REG_TGL(RCC->APB1RSTR, TIM2_RCC_PATTERN)
910 #define TIM2_ENABLE() REG_SET(RCC->APB1ENR, TIM2_RCC_PATTERN)
911 #define TIM2_DISABLE() REG_CLR(RCC->APB1ENR, TIM2_RCC_PATTERN)
912 #define TIM2_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM2_RCC_PATTERN)
913 #define TIM2_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM2_RCC_PATTERN)
914 
915 #define TIM3_RCC_PATTERN ( 0x1 << 1u )
916 #define TIM3_RESET() REG_TGL(RCC->APB1RSTR, TIM3_RCC_PATTERN)
917 #define TIM3_ENABLE() REG_SET(RCC->APB1ENR, TIM3_RCC_PATTERN)
918 #define TIM3_DISABLE() REG_CLR(RCC->APB1ENR, TIM3_RCC_PATTERN)
919 #define TIM3_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM3_RCC_PATTERN)
920 #define TIM3_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM3_RCC_PATTERN)
921 
922 #define TIM4_RCC_PATTERN ( 0x1 << 2u )
923 #define TIM4_RESET() REG_TGL(RCC->APB1RSTR, TIM4_RCC_PATTERN)
924 #define TIM4_ENABLE() REG_SET(RCC->APB1ENR, TIM4_RCC_PATTERN)
925 #define TIM4_DISABLE() REG_CLR(RCC->APB1ENR, TIM4_RCC_PATTERN)
926 #define TIM4_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM4_RCC_PATTERN)
927 #define TIM4_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM4_RCC_PATTERN)
928 
929 #define TIM5_RCC_PATTERN ( 0x1 << 3u )
930 #define TIM5_RESET() REG_TGL(RCC->APB1RSTR, TIM5_RCC_PATTERN)
931 #define TIM5_ENABLE() REG_SET(RCC->APB1ENR, TIM5_RCC_PATTERN)
932 #define TIM5_DISABLE() REG_CLR(RCC->APB1ENR, TIM5_RCC_PATTERN)
933 #define TIM5_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM5_RCC_PATTERN)
934 #define TIM5_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM5_RCC_PATTERN)
935 
936 #define TIM6_RCC_PATTERN ( 0x1 << 4u )
937 #define TIM6_RESET() REG_TGL(RCC->APB1RSTR, TIM6_RCC_PATTERN)
938 #define TIM6_ENABLE() REG_SET(RCC->APB1ENR, TIM6_RCC_PATTERN)
939 #define TIM6_DISABLE() REG_CLR(RCC->APB1ENR, TIM6_RCC_PATTERN)
940 #define TIM6_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM6_RCC_PATTERN)
941 #define TIM6_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM6_RCC_PATTERN)
942 
943 #define TIM7_RCC_PATTERN ( 0x1 << 5u )
944 #define TIM7_RESET() REG_TGL(RCC->APB1RSTR, TIM7_RCC_PATTERN)
945 #define TIM7_ENABLE() REG_SET(RCC->APB1ENR, TIM7_RCC_PATTERN)
946 #define TIM7_DISABLE() REG_CLR(RCC->APB1ENR, TIM7_RCC_PATTERN)
947 #define TIM7_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM7_RCC_PATTERN)
948 #define TIM7_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM7_RCC_PATTERN)
949 
950 #define TIM8_RCC_PATTERN ( 0x1 << 1u )
951 #define TIM8_RESET() REG_TGL(RCC->APB2RSTR, TIM8_RCC_PATTERN)
952 #define TIM8_ENABLE() REG_SET(RCC->APB2ENR, TIM8_RCC_PATTERN)
953 #define TIM8_DISABLE() REG_CLR(RCC->APB2ENR, TIM8_RCC_PATTERN)
954 #define TIM8_LP_ENABLE() REG_SET(RCC->APB2LPENR, TIM8_RCC_PATTERN)
955 #define TIM8_LP_DISABLE() REG_CLR(RCC->APB2LPENR, TIM8_RCC_PATTERN)
956 
957 #define TIM9_RCC_PATTERN ( 0x1 << 16u )
958 #define TIM9_RESET() REG_TGL(RCC->APB2RSTR, TIM9_RCC_PATTERN)
959 #define TIM9_ENABLE() REG_SET(RCC->APB2ENR, TIM9_RCC_PATTERN)
960 #define TIM9_DISABLE() REG_CLR(RCC->APB2ENR, TIM9_RCC_PATTERN)
961 #define TIM9_LP_ENABLE() REG_SET(RCC->APB2LPENR, TIM9_RCC_PATTERN)
962 #define TIM9_LP_DISABLE() REG_CLR(RCC->APB2LPENR, TIM9_RCC_PATTERN)
963 
964 #define TIM10_RCC_PATTERN ( 0x1 << 17u )
965 #define TIM10_RESET() REG_TGL(RCC->APB2RSTR, TIM10_RCC_PATTERN)
966 #define TIM10_ENABLE() REG_SET(RCC->APB2ENR, TIM10_RCC_PATTERN)
967 #define TIM10_DISABLE() REG_CLR(RCC->APB2ENR, TIM10_RCC_PATTERN)
968 #define TIM10_LP_ENABLE() REG_SET(RCC->APB2LPENR, TIM10_RCC_PATTERN)
969 #define TIM10_LP_DISABLE() REG_CLR(RCC->APB2LPENR, TIM10_RCC_PATTERN)
970 
971 #define TIM11_RCC_PATTERN ( 0x1 << 18u )
972 #define TIM11_RESET() REG_TGL(RCC->APB2RSTR, TIM11_RCC_PATTERN)
973 #define TIM11_ENABLE() REG_SET(RCC->APB2ENR, TIM11_RCC_PATTERN)
974 #define TIM11_DISABLE() REG_CLR(RCC->APB2ENR, TIM11_RCC_PATTERN)
975 #define TIM11_LP_ENABLE() REG_SET(RCC->APB2LPENR, TIM11_RCC_PATTERN)
976 #define TIM11_LP_DISABLE() REG_CLR(RCC->APB2LPENR, TIM11_RCC_PATTERN)
977 
978 #define TIM12_RCC_PATTERN ( 0x1 << 6u )
979 #define TIM12_RESET() REG_TGL(RCC->APB1RSTR, TIM12_RCC_PATTERN)
980 #define TIM12_ENABLE() REG_SET(RCC->APB1ENR, TIM12_RCC_PATTERN)
981 #define TIM12_DISABLE() REG_CLR(RCC->APB1ENR, TIM12_RCC_PATTERN)
982 #define TIM12_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM12_RCC_PATTERN)
983 #define TIM12_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM12_RCC_PATTERN)
984 
985 #define TIM13_RCC_PATTERN ( 0x1 << 7u )
986 #define TIM13_RESET() REG_TGL(RCC->APB1RSTR, TIM13_RCC_PATTERN)
987 #define TIM13_ENABLE() REG_SET(RCC->APB1ENR, TIM13_RCC_PATTERN)
988 #define TIM13_DISABLE() REG_CLR(RCC->APB1ENR, TIM13_RCC_PATTERN)
989 #define TIM13_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM13_RCC_PATTERN)
990 #define TIM13_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM13_RCC_PATTERN)
991 
992 #define TIM14_RCC_PATTERN ( 0x1 << 8u )
993 #define TIM14_RESET() REG_TGL(RCC->APB1RSTR, TIM14_RCC_PATTERN)
994 #define TIM14_ENABLE() REG_SET(RCC->APB1ENR, TIM14_RCC_PATTERN)
995 #define TIM14_DISABLE() REG_CLR(RCC->APB1ENR, TIM14_RCC_PATTERN)
996 #define TIM14_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM14_RCC_PATTERN)
997 #define TIM14_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM14_RCC_PATTERN)
998 
999 
1000 /* IWDG - independent watchdog
1001  * ------------------------------------------------------------------------- */
1002 
1009 typedef struct {
1010  volatile uint32_t KR;
1011  volatile uint32_t PR;
1012  volatile uint32_t RLR;
1013  volatile uint32_t SR;
1014 } reg_iwdg_t;
1015 
1016 
1017 /* Register macro */
1018 
1019 #ifdef TESTING
1020  extern reg_iwdg_t iwdg_testing;
1021  #define IWDG ( (reg_iwdg_t *) &iwdg_testing )
1022 #else
1023  #define IWDG ( (reg_iwdg_t *) 0x40003000 )
1024 #endif
1025 
1026 
1027 /* WWDG - window watch dog
1028  * ------------------------------------------------------------------------- */
1029 
1036 typedef struct {
1037  volatile uint32_t CR;
1038  volatile uint32_t CFR;
1039  volatile uint32_t SR;
1040 } reg_wwdg_t;
1041 
1042 
1043 /* Register macro */
1044 
1045 #ifdef TESTING
1046  extern reg_wwdg_t wwgd_testing;
1047  #define WWDG ( (reg_wwdg_t *) &wwgd_testing )
1048 #else
1049  #define WWDG ( (reg_wwdg_t *) 0x40002c00 )
1050 #endif
1051 
1052 
1053 /* Helper macros */
1054 
1055 #define WWDG_RCC_PATTERN ( 0x1 << 11u )
1056 #define WWDG_RESET() REG_TGL(RCC->APB1RSTR, WWDG_RCC_PATTERN)
1057 #define WWDG_ENABLE() REG_SET(RCC->APB1ENR, WWDG_RCC_PATTERN)
1058 #define WWDG_DISABLE() REG_CLR(RCC->APB1ENR, WWDG_RCC_PATTERN)
1059 #define WWDG_LP_ENABLE() REG_SET(RCC->APB1LPENR, WWDG_RCC_PATTERN)
1060 #define WWDG_LP_DISABLE() REG_CLR(RCC->APB1LPENR, WWDG_RCC_PATTERN)
1061 
1062 
1063 /* CRYP - cryptographic processor
1064  * ------------------------------------------------------------------------- */
1065 
1072 typedef struct {
1073  volatile uint32_t CR;
1074  volatile uint32_t SR;
1075  volatile uint32_t DIN;
1076  volatile uint32_t DOUT;
1077  volatile uint32_t DMACR;
1078  volatile uint32_t IMSCR;
1079  volatile uint32_t RISR;
1080  volatile uint32_t MISR;
1081  volatile uint32_t K0LR;
1082  volatile uint32_t K0RR;
1083  volatile uint32_t K1LR;
1084  volatile uint32_t K1RR;
1085  volatile uint32_t K2LR;
1086  volatile uint32_t K2RR;
1087  volatile uint32_t K3LR;
1088  volatile uint32_t K3RR;
1089  volatile uint32_t IV0LR;
1090  volatile uint32_t IV0RR;
1091  volatile uint32_t IV1LR;
1092  volatile uint32_t IV1RR;
1093  volatile uint32_t CSGCMCCM0R;
1094  volatile uint32_t CSGCMCCM1R;
1095  volatile uint32_t CSGCMCCM2R;
1096  volatile uint32_t CSGCMCCM3R;
1097  volatile uint32_t CSGCMCCM4R;
1098  volatile uint32_t CSGCMCCM5R;
1099  volatile uint32_t CSGCMCCM6R;
1100  volatile uint32_t CSGCMCCM7R;
1101  volatile uint32_t CSGCM0R;
1102  volatile uint32_t CSGCM1R;
1103  volatile uint32_t CSGCM2R;
1104  volatile uint32_t CSGCM3R;
1105  volatile uint32_t CSGCM4R;
1106  volatile uint32_t CSGCM5R;
1107  volatile uint32_t CSGCM6R;
1108  volatile uint32_t CSGCM7R;
1109 } reg_cryp_t;
1110 
1111 
1112 /* Register macro */
1113 
1114 #ifdef TESTING
1115  extern reg_cryp_t cryp_testing;
1116  #define CRYP ( (reg_cryp_t *) &cryp_testing )
1117 #else
1118  #define CRYP ( (reg_cryp_t *) 0x50060000 )
1119 #endif
1120 
1121 
1122 /* Helper macros */
1123 
1124 #define CRYP_RCC_PATTERN ( 0x1 << 4u )
1125 #define CRYP_RESET() REG_TGL(RCC->AHB2RSTR, CRYP_RCC_PATTERN)
1126 #define CRYP_ENABLE() REG_SET(RCC->AHB2ENR, CRYP_RCC_PATTERN)
1127 #define CRYP_DISABLE() REG_CLR(RCC->AHB2ENR, CRYP_RCC_PATTERN)
1128 #define CRYP_LP_ENABLE() REG_SET(RCC->AHB2LPENR, CRYP_RCC_PATTERN)
1129 #define CRYP_LP_DISABLE() REG_CLR(RCC->AHB2LPENR, CRYP_RCC_PATTERN)
1130 
1131 
1132 /* RNG - random number generator
1133  * ------------------------------------------------------------------------- */
1134 
1141 typedef struct {
1142  volatile uint32_t CR;
1143  volatile uint32_t SR;
1144  volatile uint32_t DR;
1145 } reg_rng_t;
1146 
1147 
1148 /* Register macro */
1149 
1150 #ifdef TESTING
1151  extern reg_rng_t rng_testing;
1152  #define RNG ( (reg_rng_t *) &rng_testing )
1153 #else
1154  #define RNG ( (reg_rng_t *) 0x50060800 )
1155 #endif
1156 
1157 
1158 /* Helper macros */
1159 
1160 #define RNG_RCC_PATTERN ( 0x1 << 6u )
1161 #define RNG_RESET() REG_TGL(RCC->AHB2RSTR, RNG_RCC_PATTERN)
1162 #define RNG_ENABLE() REG_SET(RCC->AHB2ENR, RNG_RCC_PATTERN)
1163 #define RNG_DISABLE() REG_CLR(RCC->AHB2ENR, RNG_RCC_PATTERN)
1164 #define RNG_LP_ENABLE() REG_SET(RCC->AHB2LPENR, RNG_RCC_PATTERN)
1165 #define RNG_LP_DISABLE() REG_CLR(RCC->AHB2LPENR, RNG_RCC_PATTERN)
1166 
1167 
1168 /* HASH - hashxxx
1169  * ------------------------------------------------------------------------- */
1170 
1177 typedef struct {
1178  volatile uint32_t CR;
1179  volatile uint32_t DIN;
1180  volatile uint32_t STR;
1181 // volatile uint32_t HR[5];
1182  uint32_t RESERVED1[5];
1183  volatile uint32_t IMR;
1184  volatile uint32_t SR;
1185  uint32_t RESERVED2[48];
1186  volatile uint32_t CSR[54];
1187  uint32_t RESERVED3[80];
1188  volatile uint32_t HR0;
1189  volatile uint32_t HR1;
1190  volatile uint32_t HR2;
1191  volatile uint32_t HR3;
1192  volatile uint32_t HR4;
1193  volatile uint32_t HR5;
1194  volatile uint32_t HR6;
1195  volatile uint32_t HR7;
1196 } reg_hash_t;
1197 
1198 
1199 /* Register macro */
1200 
1201 #ifdef TESTING
1202  extern reg_hash_t hash_testing;
1203  #define HASH ( (reg_hash_t *) &hash_testing )
1204 #else
1205  #define HASH ( (reg_hash_t *) 0x50060400 )
1206 #endif
1207 
1208 
1209 /* Helper macros */
1210 
1211 #define HASH_RCC_PATTERN ( 0x1 << 5u )
1212 #define HASH_RESET() REG_TGL(RCC->AHB2RSTR, HASH_RCC_PATTERN)
1213 #define HASH_ENABLE() REG_SET(RCC->AHB2ENR, HASH_RCC_PATTERN)
1214 #define HASH_DISABLE() REG_CLR(RCC->AHB2ENR, HASH_RCC_PATTERN)
1215 #define HASH_LP_ENABLE() REG_SET(RCC->AHB2LPENR, HASH_RCC_PATTERN)
1216 #define HASH_LP_DISABLE() REG_CLR(RCC->AHB2LPENR, HASH_RCC_PATTERN)
1217 
1218 
1219 /* RTC - real time clock
1220  * ------------------------------------------------------------------------- */
1221 
1228 typedef struct {
1229  volatile uint32_t TR;
1230  volatile uint32_t DR;
1231  volatile uint32_t CR;
1232  volatile uint32_t ISR;
1233  volatile uint32_t PRER;
1234  volatile uint32_t WUTR;
1235  volatile uint32_t CALIBR;
1236  volatile uint32_t ALRMAR;
1237  volatile uint32_t ALRMBR;
1238  volatile uint32_t WPR;
1239  volatile uint32_t SSR;
1240  volatile uint32_t SHIFTR;
1241  volatile uint32_t TSTR;
1242  volatile uint32_t TSDR;
1243  volatile uint32_t TSSSR;
1244  volatile uint32_t CALR;
1245  volatile uint32_t TAFCR;
1246  volatile uint32_t ALRMASSR;
1247  volatile uint32_t ALRMBSSR;
1248  uint32_t RESERVED;
1249  volatile uint32_t BKP0R;
1250  volatile uint32_t BKP1R;
1251  volatile uint32_t BKP2R;
1252  volatile uint32_t BKP3R;
1253  volatile uint32_t BKP4R;
1254  volatile uint32_t BKP5R;
1255  volatile uint32_t BKP6R;
1256  volatile uint32_t BKP7R;
1257  volatile uint32_t BKP8R;
1258  volatile uint32_t BKP9R;
1259  volatile uint32_t BKP10R;
1260  volatile uint32_t BKP11R;
1261  volatile uint32_t BKP12R;
1262  volatile uint32_t BKP13R;
1263  volatile uint32_t BKP14R;
1264  volatile uint32_t BKP15R;
1265  volatile uint32_t BKP16R;
1266  volatile uint32_t BKP17R;
1267  volatile uint32_t BKP18R;
1268  volatile uint32_t BKP19R;
1269 } reg_rtc_t;
1270 
1271 
1272 /* Register macro */
1273 
1274 #ifdef TESTING
1275  extern reg_rtc_t rtc_testing;
1276  #define RTC ( (reg_rtc_t *) &hash_testing )
1277 #else
1278  #define RTC ( (reg_rtc_t *) 0x40002800 )
1279 #endif
1280 
1281 
1282 /* I2C - inter-integrated circuit interface
1283  * ------------------------------------------------------------------------- */
1284 
1291 typedef struct {
1292  volatile uint32_t CR1;
1293  volatile uint32_t CR2;
1294  volatile uint32_t OAR1;
1295  volatile uint32_t OAR2;
1296  volatile uint32_t DR;
1297  volatile uint32_t SR1;
1298  volatile uint32_t SR2;
1299  volatile uint32_t CCR;
1300  volatile uint32_t TRISE;
1301  volatile uint32_t FLTR;
1302 } reg_i2c_t;
1303 
1304 
1305 /* Register macros */
1306 
1307 #ifdef TESTING
1308  extern reg_i2c_t i2c1_testing;
1309  extern reg_i2c_t i2c2_testing;
1310  extern reg_i2c_t i2c3_testing;
1311  #define I2C1 ( (reg_i2c_t *) &i2c1_testing )
1312  #define I2C2 ( (reg_i2c_t *) &i2c2_testing )
1313  #define I2C3 ( (reg_i2c_t *) &i2c3_testing )
1314 #else
1315  #define I2C1 ( (reg_i2c_t *) 0x40005400 )
1316  #define I2C2 ( (reg_i2c_t *) 0x40005800 )
1317  #define I2C3 ( (reg_i2c_t *) 0x40005c00 )
1318 #endif
1319 
1320 
1321 /* Helper macros */
1322 
1323 #define I2C1_RCC_PATTERN ( 0x1 << 21u )
1324 #define I2C1_RESET() REG_TGL(RCC->APB1RSTR, I2C1_RCC_PATTERN)
1325 #define I2C1_ENABLE() REG_SET(RCC->APB1ENR, I2C1_RCC_PATTERN)
1326 #define I2C1_DISABLE() REG_CLR(RCC->APB1ENR, I2C1_RCC_PATTERN)
1327 #define I2C1_LP_ENABLE() REG_SET(RCC->APB1LPENR, I2C1_RCC_PATTERN)
1328 #define I2C1_LP_DISABLE() REG_CLR(RCC->APB1LPENR, I2C1_RCC_PATTERN)
1329 
1330 #define I2C2_RCC_PATTERN ( 0x1 << 22u )
1331 #define I2C2_RESET() REG_TGL(RCC->APB1RSTR, I2C2_RCC_PATTERN)
1332 #define I2C2_ENABLE() REG_SET(RCC->APB1ENR, I2C2_RCC_PATTERN)
1333 #define I2C2_DISABLE() REG_CLR(RCC->APB1ENR, I2C2_RCC_PATTERN)
1334 #define I2C2_LP_ENABLE() REG_SET(RCC->APB1LPENR, I2C2_RCC_PATTERN)
1335 #define I2C2_LP_DISABLE() REG_CLR(RCC->APB1LPENR, I2C2_RCC_PATTERN)
1336 
1337 #define I2C3_RCC_PATTERN ( 0x1 << 23u )
1338 #define I2C3_RESET() REG_TGL(RCC->APB1RSTR, I2C3_RCC_PATTERN)
1339 #define I2C3_ENABLE() REG_SET(RCC->APB1ENR, I2C3_RCC_PATTERN)
1340 #define I2C3_DISABLE() REG_CLR(RCC->APB1ENR, I2C3_RCC_PATTERN)
1341 #define I2C3_LP_ENABLE() REG_SET(RCC->APB1LPENR, I2C3_RCC_PATTERN)
1342 #define I2C3_LP_DISABLE() REG_CLR(RCC->APB1LPENR, I2C3_RCC_PATTERN)
1343 
1344 
1345 /* SPI - serial peripheral interface
1346  * ------------------------------------------------------------------------- */
1347 
1354 typedef struct {
1355  volatile uint32_t CR1;
1356  volatile uint32_t CR2;
1357  volatile uint32_t SR;
1358  volatile uint32_t DR;
1359  volatile uint32_t CRCPR;
1360  volatile uint32_t RXCRCR;
1361  volatile uint32_t TXCRCR;
1362  volatile uint32_t I2SCFGR;
1363  volatile uint32_t I2SPR;
1364 } reg_spi_t;
1365 
1366 
1367 /* Register macros */
1368 
1369 #ifdef TESTING
1370  extern reg_spi_t spi1_testing;
1371  extern reg_spi_t spi2_testing;
1372  extern reg_spi_t spi3_testing;
1373  extern reg_spi_t spi4_testing;
1374  extern reg_spi_t spi5_testing;
1375  extern reg_spi_t spi6_testing;
1376  #define SPI1 ( (reg_spi_t *) &spi1_testing )
1377  #define SPI2 ( (reg_spi_t *) &spi2_testing )
1378  #define SPI3 ( (reg_spi_t *) &spi3_testing )
1379  #define SPI4 ( (reg_spi_t *) &spi4_testing )
1380  #define SPI5 ( (reg_spi_t *) &spi5_testing )
1381  #define SPI6 ( (reg_spi_t *) &spi6_testing )
1382 #else
1383  #define SPI1 ( (reg_spi_t *) 0x40013000 )
1384  #define SPI2 ( (reg_spi_t *) 0x40003800 )
1385  #define SPI3 ( (reg_spi_t *) 0x40003c00 )
1386  #define SPI4 ( (reg_spi_t *) 0x40013400 )
1387  #define SPI5 ( (reg_spi_t *) 0x40015000 )
1388  #define SPI6 ( (reg_spi_t *) 0x40015400 )
1389 #endif
1390 
1391 
1392 /* Helper macros */
1393 
1394 #define SPI1_RCC_PATTERN ( 0x1 << 12u )
1395 #define SPI1_RESET() REG_TGL(RCC->APB2RSTR, SPI1_RCC_PATTERN)
1396 #define SPI1_ENABLE() REG_SET(RCC->APB2ENR, SPI1_RCC_PATTERN)
1397 #define SPI1_DISABLE() REG_CLR(RCC->APB2ENR, SPI1_RCC_PATTERN)
1398 #define SPI1_LP_ENABLE() REG_SET(RCC->APB2LPENR, SPI1_RCC_PATTERN)
1399 #define SPI1_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SPI1_RCC_PATTERN)
1400 
1401 #define SPI2_RCC_PATTERN ( 0x1 << 14u )
1402 #define SPI2_RESET() REG_TGL(RCC->APB1RSTR, SPI2_RCC_PATTERN)
1403 #define SPI2_ENABLE() REG_SET(RCC->APB1ENR, SPI2_RCC_PATTERN)
1404 #define SPI2_DISABLE() REG_CLR(RCC->APB1ENR, SPI2_RCC_PATTERN)
1405 #define SPI2_LP_ENABLE() REG_SET(RCC->APB1LPENR, SPI2_RCC_PATTERN)
1406 #define SPI2_LP_DISABLE() REG_CLR(RCC->APB1LPENR, SPI2_RCC_PATTERN)
1407 
1408 #define SPI3_RCC_PATTERN ( 0x1 << 15u )
1409 #define SPI3_RESET() REG_TGL(RCC->APB1RSTR, SPI3_RCC_PATTERN)
1410 #define SPI3_ENABLE() REG_SET(RCC->APB1ENR, SPI3_RCC_PATTERN)
1411 #define SPI3_DISABLE() REG_CLR(RCC->APB1ENR, SPI3_RCC_PATTERN)
1412 #define SPI3_LP_ENABLE() REG_SET(RCC->APB1LPENR, SPI3_RCC_PATTERN)
1413 #define SPI3_LP_DISABLE() REG_CLR(RCC->APB1LPENR, SPI3_RCC_PATTERN)
1414 
1415 #define SPI4_RCC_PATTERN ( 0x1 << 13u )
1416 #define SPI4_RESET() REG_TGL(RCC->APB2RSTR, SPI4_RCC_PATTERN)
1417 #define SPI4_ENABLE() REG_SET(RCC->APB2ENR, SPI4_RCC_PATTERN)
1418 #define SPI4_DISABLE() REG_CLR(RCC->APB2ENR, SPI4_RCC_PATTERN)
1419 #define SPI4_LP_ENABLE() REG_SET(RCC->APB2LPENR, SPI4_RCC_PATTERN)
1420 #define SPI4_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SPI4_RCC_PATTERN)
1421 
1422 #define SPI5_RCC_PATTERN ( 0x1 << 20u )
1423 #define SPI5_RESET() REG_TGL(RCC->APB2RSTR, SPI5_RCC_PATTERN)
1424 #define SPI5_ENABLE() REG_SET(RCC->APB2ENR, SPI5_RCC_PATTERN)
1425 #define SPI5_DISABLE() REG_CLR(RCC->APB2ENR, SPI5_RCC_PATTERN)
1426 #define SPI5_LP_ENABLE() REG_SET(RCC->APB2LPENR, SPI5_RCC_PATTERN)
1427 #define SPI5_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SPI5_RCC_PATTERN)
1428 
1429 #define SPI6_RCC_PATTERN ( 0x1 << 21u )
1430 #define SPI6_RESET() REG_TGL(RCC->APB2RSTR, SPI6_RCC_PATTERN)
1431 #define SPI6_ENABLE() REG_SET(RCC->APB2ENR, SPI6_RCC_PATTERN)
1432 #define SPI6_DISABLE() REG_CLR(RCC->APB2ENR, SPI6_RCC_PATTERN)
1433 #define SPI6_LP_ENABLE() REG_SET(RCC->APB2LPENR, SPI6_RCC_PATTERN)
1434 #define SPI6_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SPI6_RCC_PATTERN)
1435 
1436 
1437 /* SAI - sxxx audio interface
1438  * ------------------------------------------------------------------------- */
1439 
1446 typedef struct {
1447  volatile uint32_t CR1;
1448  volatile uint32_t CR2;
1449  volatile uint32_t FRCR;
1450  volatile uint32_t SLOTR;
1451  volatile uint32_t IM;
1452  volatile uint32_t SR;
1453  volatile uint32_t CLRFR;
1454  volatile uint32_t DR;
1455 } reg_sai_block_t;
1456 
1457 
1464 typedef struct {
1465  volatile reg_sai_block_t BLOCK1;
1466  volatile reg_sai_block_t BLOCK2;
1467 } reg_sai_t;
1468 
1469 
1470 /* Register macros */
1471 
1472 #ifdef TESTING
1473  extern reg_sai_t sat1_testing;
1474  #define SAI1 ( (reg_sai_t *) &sat1_testing )
1475 #else
1476  #define SAI1 ( (reg_sai_t *) 0x40015800 )
1477 #endif
1478 
1479 /* Helper macros */
1480 
1481 #define SAI1_RCC_PATTERN ( 0x1 << 22u )
1482 #define SAI1_RESET() REG_TGL(RCC->APB2RSTR, SAI1_RCC_PATTERN)
1483 #define SAI1_ENABLE() REG_SET(RCC->APB2ENR, SAI1_RCC_PATTERN)
1484 #define SAI1_DISABLE() REG_CLR(RCC->APB2ENR, SAI1_RCC_PATTERN)
1485 #define SAI1_LP_ENABLE() REG_SET(RCC->APB2LPENR, SAI1_RCC_PATTERN)
1486 #define SAI1_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SAI1_RCC_PATTERN)
1487 
1488 
1489 /* USART - universal synchronous/asynchronous receiver transmitter
1490  * ------------------------------------------------------------------------- */
1491 
1498 typedef struct {
1499  volatile uint32_t SR;
1500  volatile uint32_t DR;
1501  volatile uint32_t BRR;
1502  volatile uint32_t CR1;
1503  volatile uint32_t CR2;
1504  volatile uint32_t CR3;
1505  volatile uint32_t GPTR;
1506 } reg_usart_t;
1507 
1508 
1509 /* Register macros */
1510 
1511 #ifdef TESTING
1512  extern reg_usart_t usart1_testing;
1513  extern reg_usart_t usart2_testing;
1514  extern reg_usart_t usart3_testing;
1515  extern reg_usart_t uart4_testing;
1516  extern reg_usart_t uart5_testing;
1517  extern reg_usart_t usart6_testing;
1518  extern reg_usart_t usart7_testing;
1519  extern reg_usart_t usart8_testing;
1520  #define USART1 ( (reg_usart_t *) &usart1_testing )
1521  #define USART2 ( (reg_usart_t *) &usart2_testing )
1522  #define USART3 ( (reg_usart_t *) &usart3_testing )
1523  #define UART4 ( (reg_usart_t *) &uart4_testing )
1524  #define UART5 ( (reg_usart_t *) &uart5_testing )
1525  #define USART6 ( (reg_usart_t *) &usart6_testing )
1526  #define USART7 ( (reg_usart_t *) &usart7_testing )
1527  #define USART8 ( (reg_usart_t *) &usart8_testing )
1528 #else
1529  #define USART1 ( (reg_usart_t *) 0x40011000 )
1530  #define USART2 ( (reg_usart_t *) 0x40004400 )
1531  #define USART3 ( (reg_usart_t *) 0x40004800 )
1532  #define UART4 ( (reg_usart_t *) 0x40004c00 )
1533  #define UART5 ( (reg_usart_t *) 0x40005000 )
1534  #define USART6 ( (reg_usart_t *) 0x40011400 )
1535  #define USART7 ( (reg_usart_t *) 0x40007800 )
1536  #define USART8 ( (reg_usart_t *) 0x40007c00 )
1537 #endif
1538 
1539 
1540 /* Helper macros */
1541 
1542 #define USART1_RCC_PATTERN ( 0x1 << 4u )
1543 #define USART1_RESET() REG_TGL(RCC->APB2RSTR, USART1_RCC_PATTERN)
1544 #define USART1_ENABLE() REG_SET(RCC->APB2ENR, USART1_RCC_PATTERN)
1545 #define USART1_DISABLE() REG_CLR(RCC->APB2ENR, USART1_RCC_PATTERN)
1546 #define USART1_LP_ENABLE() REG_SET(RCC->APB2LPENR, USART1_RCC_PATTERN)
1547 #define USART1_LP_DISABLE() REG_CLR(RCC->APB2LPENR, USART1_RCC_PATTERN)
1548 
1549 #define USART2_RCC_PATTERN ( 0x1 << 17u )
1550 #define USART2_RESET() REG_TGL(RCC->APB1RSTR, USART2_RCC_PATTERN)
1551 #define USART2_ENABLE() REG_SET(RCC->APB1ENR, USART2_RCC_PATTERN)
1552 #define USART2_DISABLE() REG_CLR(RCC->APB1ENR, USART2_RCC_PATTERN)
1553 #define USART2_LP_ENABLE() REG_SET(RCC->APB1LPENR, USART2_RCC_PATTERN)
1554 #define USART2_LP_DISABLE() REG_CLR(RCC->APB1LPENR, USART2_RCC_PATTERN)
1555 
1556 #define USART3_RCC_PATTERN ( 0x1 << 18u )
1557 #define USART3_RESET() REG_TGL(RCC->APB1RSTR, USART3_RCC_PATTERN)
1558 #define USART3_ENABLE() REG_SET(RCC->APB1ENR, USART3_RCC_PATTERN)
1559 #define USART3_DISABLE() REG_CLR(RCC->APB1ENR, USART3_RCC_PATTERN)
1560 #define USART3_LP_ENABLE() REG_SET(RCC->APB1LPENR, USART3_RCC_PATTERN)
1561 #define USART3_LP_DISABLE() REG_CLR(RCC->APB1LPENR, USART3_RCC_PATTERN)
1562 
1563 #define UART4_RCC_PATTERN ( 0x1 << 19u )
1564 #define UART4_RESET() REG_TGL(RCC->APB1RSTR, UART4_RCC_PATTERN)
1565 #define UART4_ENABLE() REG_SET(RCC->APB1ENR, UART4_RCC_PATTERN)
1566 #define UART4_DISABLE() REG_CLR(RCC->APB1ENR, UART4_RCC_PATTERN)
1567 #define UART4_LP_ENABLE() REG_SET(RCC->APB1LPENR, UART4_RCC_PATTERN)
1568 #define UART4_LP_DISABLE() REG_CLR(RCC->APB1LPENR, UART4_RCC_PATTERN)
1569 
1570 #define UART5_RCC_PATTERN ( 0x1 << 20u )
1571 #define UART5_RESET() REG_TGL(RCC->APB1RSTR, UART5_RCC_PATTERN)
1572 #define UART5_ENABLE() REG_SET(RCC->APB1ENR, UART5_RCC_PATTERN)
1573 #define UART5_DISABLE() REG_CLR(RCC->APB1ENR, UART5_RCC_PATTERN)
1574 #define UART5_LP_ENABLE() REG_SET(RCC->APB1LPENR, UART5_RCC_PATTERN)
1575 #define UART5_LP_DISABLE() REG_CLR(RCC->APB1LPENR, UART5_RCC_PATTERN)
1576 
1577 #define USART6_RCC_PATTERN ( 0x1 << 5u )
1578 #define USART6_RESET() REG_TGL(RCC->APB2RSTR, USART6_RCC_PATTERN)
1579 #define USART6_ENABLE() REG_SET(RCC->APB2ENR, USART6_RCC_PATTERN)
1580 #define USART6_DISABLE() REG_CLR(RCC->APB2ENR, USART6_RCC_PATTERN)
1581 #define USART6_LP_ENABLE() REG_SET(RCC->APB2LPENR, USART6_RCC_PATTERN)
1582 #define USART6_LP_DISABLE() REG_CLR(RCC->APB2LPENR, USART6_RCC_PATTERN)
1583 
1584 #define USART7_RCC_PATTERN ( 0x1 << 30u )
1585 #define USART7_RESET() REG_TGL(RCC->APB1RSTR, USART7_RCC_PATTERN)
1586 #define USART7_ENABLE() REG_SET(RCC->APB1ENR, USART7_RCC_PATTERN)
1587 #define USART7_DISABLE() REG_CLR(RCC->APB1ENR, USART7_RCC_PATTERN)
1588 #define USART7_LP_ENABLE() REG_SET(RCC->APB1LPENR, USART7_RCC_PATTERN)
1589 #define USART7_LP_DISABLE() REG_CLR(RCC->APB1LPENR, USART7_RCC_PATTERN)
1590 
1591 #define USART8_RCC_PATTERN ( 0x1 << 31u )
1592 #define USART8_RESET() REG_TGL(RCC->APB1RSTR, USART8_RCC_PATTERN)
1593 #define USART8_ENABLE() REG_SET(RCC->APB1ENR, USART8_RCC_PATTERN)
1594 #define USART8_DISABLE() REG_CLR(RCC->APB1ENR, USART8_RCC_PATTERN)
1595 #define USART8_LP_ENABLE() REG_SET(RCC->APB1LPENR, USART8_RCC_PATTERN)
1596 #define USART8_LP_DISABLE() REG_CLR(RCC->APB1LPENR, USART8_RCC_PATTERN)
1597 
1598 
1599 /* SDIO - secure digital input output
1600  * ------------------------------------------------------------------------- */
1601 
1608 typedef struct {
1609  volatile uint32_t POWER;
1610  volatile uint32_t CLKCR;
1611  volatile uint32_t ARG;
1612  volatile uint32_t CMD;
1613  volatile uint32_t RESPCMD;
1614  volatile uint32_t RESP1;
1615  volatile uint32_t RESP2;
1616  volatile uint32_t RESP3;
1617  volatile uint32_t RESP4;
1618  volatile uint32_t DTIMER;
1619  volatile uint32_t DLEN;
1620  volatile uint32_t DCTRL;
1621  volatile uint32_t DCOUNT;
1622  volatile uint32_t STA;
1623  volatile uint32_t ICR;
1624  volatile uint32_t MASK;
1625  uint32_t RESERVED[2];
1626  volatile uint32_t FIFOCNT;
1627  volatile uint32_t FIFO;
1628 } reg_sdio_t;
1629 
1630 
1631 /* Register macros */
1632 
1633 #ifdef TESTING
1634  extern reg_sdio_t sdio_testing;
1635  #define SDIO ( (reg_sdio_t *) &sdio_testing )
1636 #else
1637  #define SDIO ( (reg_sdio_t *) 0x40006400 )
1638 #endif
1639 
1640 /* Helper macros */
1641 
1642 #define SDIO_RCC_PATTERN ( 0x1 << 11u )
1643 #define SDIO_RESET() REG_TGL(RCC->APB2RSTR, SDIO_RCC_PATTERN)
1644 #define SDIO_ENABLE() REG_SET(RCC->APB2ENR, SDIO_RCC_PATTERN)
1645 #define SDIO_DISABLE() REG_CLR(RCC->APB2ENR, SDIO_RCC_PATTERN)
1646 #define SDIO_LP_ENABLE() REG_SET(RCC->APB2LPENR, SDIO_RCC_PATTERN)
1647 #define SDIO_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SDIO_RCC_PATTERN)
1648 
1649 
1650 /* CAN - cxxx
1651  * ------------------------------------------------------------------------- */
1652 
1659 typedef struct {
1660  volatile uint32_t MCR;
1661  volatile uint32_t MSR;
1662  volatile uint32_t TSR;
1663  volatile uint32_t RF0R;
1664  volatile uint32_t RF1R;
1665  volatile uint32_t IER;
1666  volatile uint32_t ESR;
1667  volatile uint32_t BTR;
1668  uint32_t RESERVED1[88];
1669  volatile uint32_t TI0R;
1670  volatile uint32_t TDT0R;
1672  volatile uint32_t TDL0R;
1673  volatile uint32_t TDH0R;
1674  volatile uint32_t TI1R;
1675  volatile uint32_t TDT1R;
1677  volatile uint32_t TDL1R;
1678  volatile uint32_t TDH1R;
1679  volatile uint32_t TI2R;
1680  volatile uint32_t TDT2R;
1682  volatile uint32_t TDL2R;
1683  volatile uint32_t TDH2R;
1684  volatile uint32_t RI0R;
1685  volatile uint32_t RDT0R;
1687  volatile uint32_t RDL0R;
1688  volatile uint32_t RDH0R;
1689  volatile uint32_t RI1R;
1690  volatile uint32_t RDT1R;
1692  volatile uint32_t RDL1R;
1693  volatile uint32_t RDH1R;
1694  uint32_t RESERVED2[12];
1695  volatile uint32_t FMR;
1696  volatile uint32_t FM1R;
1697  uint32_t RESERVED3;
1698  volatile uint32_t FS1R;
1699  uint32_t RESERVED4;
1700  volatile uint32_t FFA1R;
1701  uint32_t RESERVED5;
1702  volatile uint32_t FA1R;
1703  uint32_t RESERVED6[8];
1704  volatile uint32_t FR[28][2];
1706 } reg_can_t;
1707 
1708 
1709 /* Register macros */
1710 
1711 #ifdef TESTING
1712  extern reg_can_t can1_testing;
1713  extern reg_can_t can2_testing;
1714  #define CAN1 ( (reg_can_t *) &can1_testing )
1715  #define CAN2 ( (reg_can_t *) &can2_testing )
1716 #else
1717  #define CAN1 ( (reg_can_t *) 0x40006400 )
1718  #define CAN2 ( (reg_can_t *) 0x40006800 )
1719 #endif
1720 
1721 
1722 /* Helper macros */
1723 
1724 #define CAN1_RCC_PATTERN ( 0x1 << 25u )
1725 #define CAN1_RESET() REG_TGL(RCC->APB1RSTR, CAN1_RCC_PATTERN)
1726 #define CAN1_ENABLE() REG_SET(RCC->APB1ENR, CAN1_RCC_PATTERN)
1727 #define CAN1_DISABLE() REG_CLR(RCC->APB1ENR, CAN1_RCC_PATTERN)
1728 #define CAN1_LP_ENABLE() REG_SET(RCC->APB1LPENR, CAN1_RCC_PATTERN)
1729 #define CAN1_LP_DISABLE() REG_CLR(RCC->APB1LPENR, CAN1_RCC_PATTERN)
1730 
1731 #define CAN2_RCC_PATTERN ( 0x1 << 26u )
1732 #define CAN2_RESET() REG_TGL(RCC->APB1RSTR, CAN2_RCC_PATTERN)
1733 #define CAN2_ENABLE() REG_SET(RCC->APB1ENR, CAN2_RCC_PATTERN)
1734 #define CAN2_DISABLE() REG_CLR(RCC->APB1ENR, CAN2_RCC_PATTERN)
1735 #define CAN2_LP_ENABLE() REG_SET(RCC->APB1LPENR, CAN2_RCC_PATTERN)
1736 #define CAN2_LP_DISABLE() REG_CLR(RCC->APB1LPENR, CAN2_RCC_PATTERN)
1737 
1738 
1739 /* FMC - flexible memory controller
1740  * ------------------------------------------------------------------------- */
1741 
1746 typedef struct {
1747  volatile uint32_t BCR1;
1748  volatile uint32_t BTR1;
1749  volatile uint32_t BCR2;
1750  volatile uint32_t BTR2;
1751  volatile uint32_t BCR3;
1752  volatile uint32_t BTR3;
1753  volatile uint32_t BCR4;
1754  volatile uint32_t BTR4;
1755  uint32_t RESERVED1[57];
1756  volatile uint32_t BWTR1;
1757  uint32_t RESERVED2;
1758  volatile uint32_t BWTR2;
1759  uint32_t RESERVED3;
1760  volatile uint32_t BWTR3;
1761  uint32_t RESERVED4;
1762  volatile uint32_t BWTR4;
1763 } reg_fmc_sram_t;
1764 
1765 
1772 typedef struct {
1773  reg_fmc_sram_t SRAM;
1774 } reg_fmc_t;
1775 
1776 
1777 /* Register macro */
1778 
1779 #ifdef TESTING
1780  extern reg_fmc_t fmc_testing;
1781  #define FMC ( (reg_fmc_t *) &fmc_testing )
1782 #else
1783  #define FMC ( (reg_fmc_t *) 0xa0000000 )
1784 #endif
1785 
1786 
1787 /* Helper macros */
1788 
1789 #define FMC_RCC_PATTERN ( 0x1 << 0u )
1790 #define FMC_RESET() REG_TGL(RCC->AHB3RSTR, FMC_RCC_PATTERN)
1791 #define FMC_ENABLE() REG_SET(RCC->AHB3ENR, FMC_RCC_PATTERN)
1792 #define FMC_DISABLE() REG_CLR(RCC->AHB3ENR, FMC_RCC_PATTERN)
1793 #define FMC_LP_ENABLE() REG_SET(RCC->AHB3LPENR, FMC_RCC_PATTERN)
1794 #define FMC_LP_DISABLE() REG_CLR(RCC->AHB3LPENR, FMC_RCC_PATTERN)
1795 
1796 
1797 /* MPU - memory protection unit
1798  * ------------------------------------------------------------------------- */
1799 
1806 typedef struct {
1807  volatile uint32_t TYPER;
1808  volatile uint32_t CTRL;
1809  volatile uint32_t RNR;
1810  volatile uint32_t RBAR;
1811  volatile uint32_t RASR;
1812 } reg_mpu_t;
1813 
1814 
1815 /* Register macro */
1816 
1817 #ifdef TESTING
1818  extern reg_mpu_t mpu_testing;
1819  #define MPU ( (reg_mpu_t *) &mpu_testing )
1820 #else
1821  #define MPU ( (reg_mpu_t *) 0xe000ed90 )
1822 #endif
1823 
1824 
1825 /* SCB - system control block
1826  * ------------------------------------------------------------------------- */
1827 
1834 typedef struct {
1835  volatile uint32_t CPUID;
1836  volatile uint32_t ICSR;
1837  volatile uint32_t VTOR;
1838  volatile uint32_t AIRCR;
1839  volatile uint32_t SCR;
1840  volatile uint32_t CCR;
1841  volatile uint32_t SHPR1;
1842  volatile uint32_t SHPR2;
1843  volatile uint32_t SHPR3;
1844  volatile uint32_t SHCSR;
1845  volatile uint32_t CFSR;
1849  volatile uint32_t HFSR;
1850  uint32_t RESERVED;
1851  volatile uint32_t MMAR;
1852  volatile uint32_t BFAR;
1853  volatile uint32_t AFSR;
1854 } reg_scb_t;
1855 
1856 
1857 /* Register macro */
1858 
1859 #ifdef TESTING
1860  extern reg_scb_t scb_testing;
1861  #define SCB ( (reg_scb_t *) &scb_testing )
1862 #else
1863  #define SCB ( (reg_scb_t *) 0xe000ed00 )
1864 #endif
1865 
1866 
1867 /* STK - system tick timer
1868  * ------------------------------------------------------------------------- */
1869 
1876 typedef struct {
1877  volatile uint32_t CTRL;
1878  volatile uint32_t LOAD;
1879  volatile uint32_t VAL;
1880  volatile uint32_t CALIB;
1881 } reg_stk_t;
1882 
1883 
1884 /* Register macro */
1885 
1886 #ifdef TESTING
1887  extern reg_stk_t stk_testing;
1888  #define STK ( (reg_stk_t *) &stk_testing )
1889 #else
1890  #define STK ( (reg_stk_t *) 0xe000e010 )
1891 #endif
1892 
1893 
1894 /* FPU - floating point unit
1895  * ------------------------------------------------------------------------- */
1896 
1903 typedef struct {
1904  volatile uint32_t CPACR;
1905  uint32_t RESERVED[106];
1906  volatile uint32_t FPCCR;
1907  volatile uint32_t FPCAR;
1908  volatile uint32_t FPDSCR;
1909 } reg_fpu_t;
1910 
1911 
1912 /* Register macro */
1913 
1914 #ifdef TESTING
1915  extern reg_fpu_t fpu_testing;
1916  #define FPU ( (reg_fpu_t *) &fpu_testing )
1917 #else
1918  #define FPU ( (reg_fpu_t *) 0xe000ed88 )
1919 #endif
1920 
1921 
1922 /* DBG - debug support
1923  * ------------------------------------------------------------------------- */
1924 
1931 typedef struct {
1932  volatile uint32_t IDCODE;
1933  volatile uint32_t CR;
1934  volatile uint32_t APB1_FZ;
1935  volatile uint32_t APB2_FZ;
1936 } reg_dbg_t;
1937 
1938 
1939 /* Register macro */
1940 
1941 #ifdef TESTING
1942  extern reg_dbg_t dbg_testing;
1943  #define DBG ( (reg_dbg_t *) &dbg_testing )
1944 #else
1945  #define DBG ( (reg_dbg_t *) 0xe0042000 )
1946 #endif
1947 
1948 
1949 /* SRAM - static RAM
1950  * ------------------------------------------------------------------------- */
1951 
1952 /* Helper macros */
1953 
1954 #define SRAM1_RCC_PATTERN ( 0x1 << 16u )
1955 #define SRAM1_LP_ENABLE() REG_SET(RCC->AHB1LPENR, SRAM1_RCC_PATTERN)
1956 #define SRAM1_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, SRAM1_RCC_PATTERN)
1957 
1958 #define SRAM2_RCC_PATTERN ( 0x1 << 17u )
1959 #define SRAM2_LP_ENABLE() REG_SET(RCC->AHB1LPENR, SRAM2_RCC_PATTERN)
1960 #define SRAM2_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, SRAM2_RCC_PATTERN)
1961 
1962 #define SRAM3_RCC_PATTERN ( 0x1 << 19u )
1963 #define SRAM3_LP_ENABLE() REG_SET(RCC->AHB1LPENR, SRAM3_RCC_PATTERN)
1964 #define SRAM3_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, SRAM3_RCC_PATTERN)
1965 
1966 
1967 /* BKPSRAM - backup static RAM
1968  * ------------------------------------------------------------------------- */
1969 
1970 /* Helper macros */
1971 
1972 #define BKPSRAM_RCC_PATTERN ( 0x1 << 18u )
1973 #define BKPSRAM_ENABLE() REG_SET(RCC->AHB3ENR, BKPSRAM_RCC_PATTERN)
1974 #define BKPSRAM_DISABLE() REG_CLR(RCC->AHB3ENR, BKPSRAM_RCC_PATTERN)
1975 #define BKPSRAM_LP_ENABLE() REG_SET(RCC->AHB1LPENR, BKPSRAM_RCC_PATTERN)
1976 #define BKPSRAM_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, BKPSRAM_RCC_PATTERN)
1977 
1978 
1979 /* CCM - core coupled memory
1980  * ------------------------------------------------------------------------- */
1981 
1982 /* Helper macros */
1983 
1984 #define CCM_RCC_PATTERN ( 0x1 << 20u )
1985 #define CCM_ENABLE() REG_SET(RCC->AHB1ENR, CCM_RCC_PATTERN)
1986 #define CCM_DISABLE() REG_CLR(RCC->AHB1ENR, CCM_RCC_PATTERN)
1987 
1988 
1989 #endif
reg_i2c_t::CCR
volatile uint32_t CCR
Definition: reg_stm32f4xx.h:1299
reg_dma2d_t::BGPFCCR
volatile uint32_t BGPFCCR
Definition: reg_stm32f4xx.h:449
reg_hash_t::HR7
volatile uint32_t HR7
Definition: reg_stm32f4xx.h:1195
reg_rtc_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:1231
reg_cryp_t::MISR
volatile uint32_t MISR
Definition: reg_stm32f4xx.h:1080
reg_fpu_t::FPDSCR
volatile uint32_t FPDSCR
Definition: reg_stm32f4xx.h:1908
reg_rtc_t::BKP15R
volatile uint32_t BKP15R
Definition: reg_stm32f4xx.h:1264
reg_tim_t::DCR
volatile uint32_t DCR
Definition: reg_stm32f4xx.h:843
reg_crc_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:127
reg_wwdg_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:1037
reg_cryp_t::K2LR
volatile uint32_t K2LR
Definition: reg_stm32f4xx.h:1085
reg_rcc_t::BDCR
volatile uint32_t BDCR
Definition: reg_stm32f4xx.h:70
reg_exti_t::EMR
volatile uint32_t EMR
Definition: reg_stm32f4xx.h:540
reg_rcc_t::AHB2ENR
volatile uint32_t AHB2ENR
Definition: reg_stm32f4xx.h:57
reg_ltdc_lc_t::CACR
volatile uint32_t CACR
Definition: reg_stm32f4xx.h:757
reg_dma_stream_t::M0AR
volatile uint32_t M0AR
Definition: reg_stm32f4xx.h:381
reg_dcmi_t::ESUR
volatile uint32_t ESUR
Definition: reg_stm32f4xx.h:717
reg_tim_t::CCR1
volatile uint32_t CCR1
Definition: reg_stm32f4xx.h:838
reg_sdio_t::DLEN
volatile uint32_t DLEN
Definition: reg_stm32f4xx.h:1619
reg_cryp_t::RISR
volatile uint32_t RISR
Definition: reg_stm32f4xx.h:1079
reg_dac_t::DHR12L2
volatile uint32_t DHR12L2
Definition: reg_stm32f4xx.h:669
reg_dma_stream_t::PAR
volatile uint32_t PAR
Definition: reg_stm32f4xx.h:380
reg_exti_t::SWIER
volatile uint32_t SWIER
Definition: reg_stm32f4xx.h:543
reg_dma2d_t::FGCOLR
volatile uint32_t FGCOLR
Definition: reg_stm32f4xx.h:448
reg_tim_t::SMCR
volatile uint32_t SMCR
Definition: reg_stm32f4xx.h:827
reg_flash_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:101
reg_ltdc_t::CDSR
volatile uint32_t CDSR
Definition: reg_stm32f4xx.h:787
reg_gpio_t::ODR
volatile uint32_t ODR
Definition: reg_stm32f4xx.h:200
reg_dcmi_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:711
reg_sai_block_t::CR1
volatile uint32_t CR1
Definition: reg_stm32f4xx.h:1447
reg_flash_t::OPTCR
volatile uint32_t OPTCR
Definition: reg_stm32f4xx.h:103
reg_stk_t::CTRL
volatile uint32_t CTRL
Definition: reg_stm32f4xx.h:1877
reg_rtc_t::BKP10R
volatile uint32_t BKP10R
Definition: reg_stm32f4xx.h:1259
reg_usart_t::DR
volatile uint32_t DR
Definition: reg_stm32f4xx.h:1500
reg_hash_t
Representation of HASH register.
Definition: reg_stm32f4xx.h:1177
reg_rcc_t::AHB3RSTR
volatile uint32_t AHB3RSTR
Definition: reg_stm32f4xx.h:51
reg_nvic_t::IABR0
volatile uint32_t IABR0
Definition: reg_stm32f4xx.h:509
reg_ltdc_t::BPCR
volatile uint32_t BPCR
Definition: reg_stm32f4xx.h:776
reg_rtc_t::BKP17R
volatile uint32_t BKP17R
Definition: reg_stm32f4xx.h:1266
reg_stk_t::LOAD
volatile uint32_t LOAD
Definition: reg_stm32f4xx.h:1878
reg_sai_block_t::CLRFR
volatile uint32_t CLRFR
Definition: reg_stm32f4xx.h:1453
reg_rcc_t::PLLI2SCFGR
volatile uint32_t PLLI2SCFGR
Definition: reg_stm32f4xx.h:74
reg_dac_t::DHR12RD
volatile uint32_t DHR12RD
Definition: reg_stm32f4xx.h:671
reg_tim_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:829
reg_mpu_t::TYPER
volatile uint32_t TYPER
Definition: reg_stm32f4xx.h:1807
reg_sdio_t::CLKCR
volatile uint32_t CLKCR
Definition: reg_stm32f4xx.h:1610
reg_dma_stream_t
Representation of DMA stream register.
Definition: reg_stm32f4xx.h:377
reg_scb_t::CCR
volatile uint32_t CCR
Definition: reg_stm32f4xx.h:1840
reg_iwdg_t::PR
volatile uint32_t PR
Definition: reg_stm32f4xx.h:1011
reg_sai_block_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:1452
reg_scb_t::BFAR
volatile uint32_t BFAR
Definition: reg_stm32f4xx.h:1852
reg_rtc_t::SHIFTR
volatile uint32_t SHIFTR
Definition: reg_stm32f4xx.h:1240
reg_stk_t::CALIB
volatile uint32_t CALIB
Definition: reg_stm32f4xx.h:1880
reg_fpu_t
Representation of FPU register.
Definition: reg_stm32f4xx.h:1903
reg_can_t::FM1R
volatile uint32_t FM1R
Definition: reg_stm32f4xx.h:1696
reg_pwr_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:161
reg_gpio_t::OTYPER
volatile uint32_t OTYPER
Definition: reg_stm32f4xx.h:196
reg_flash_t::ACR
volatile uint32_t ACR
Definition: reg_stm32f4xx.h:98
reg_spi_t::RXCRCR
volatile uint32_t RXCRCR
Definition: reg_stm32f4xx.h:1360
reg_crc_t::DR
volatile uint32_t DR
Definition: reg_stm32f4xx.h:125
reg_dma2d_t::LWR
volatile uint32_t LWR
Definition: reg_stm32f4xx.h:458
reg_mpu_t::CTRL
volatile uint32_t CTRL
Definition: reg_stm32f4xx.h:1808
reg_rtc_t::BKP16R
volatile uint32_t BKP16R
Definition: reg_stm32f4xx.h:1265
reg_dbg_t::IDCODE
volatile uint32_t IDCODE
Definition: reg_stm32f4xx.h:1932
reg_rtc_t::BKP19R
volatile uint32_t BKP19R
Definition: reg_stm32f4xx.h:1268
reg_can_t::TDT2R
volatile uint32_t TDT2R
Definition: reg_stm32f4xx.h:1680
reg_syscfg_t::EXTICR2
volatile uint32_t EXTICR2
Definition: reg_stm32f4xx.h:342
reg_rcc_t::APB1RSTR
volatile uint32_t APB1RSTR
Definition: reg_stm32f4xx.h:53
reg_can_t::TDL1R
volatile uint32_t TDL1R
Definition: reg_stm32f4xx.h:1677
reg_hash_t::IMR
volatile uint32_t IMR
Definition: reg_stm32f4xx.h:1183
reg_can_t::RDT0R
volatile uint32_t RDT0R
Definition: reg_stm32f4xx.h:1685
reg_tim_t::EGR
volatile uint32_t EGR
Definition: reg_stm32f4xx.h:830
reg_dac_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:676
reg_dac_t::DHR12R2
volatile uint32_t DHR12R2
Definition: reg_stm32f4xx.h:668
reg_nvic_t::ICPR1
volatile uint32_t ICPR1
Definition: reg_stm32f4xx.h:506
reg_usart_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:1499
reg_ltdc_t::SRCR
volatile uint32_t SRCR
Definition: reg_stm32f4xx.h:780
reg_hash_t::HR0
volatile uint32_t HR0
Definition: reg_stm32f4xx.h:1188
reg_dma2d_t::FGOR
volatile uint32_t FGOR
Definition: reg_stm32f4xx.h:444
reg_tim_t::CR1
volatile uint32_t CR1
Definition: reg_stm32f4xx.h:825
reg_hash_t::HR4
volatile uint32_t HR4
Definition: reg_stm32f4xx.h:1192
reg_syscfg_t::EXTICR1
volatile uint32_t EXTICR1
Definition: reg_stm32f4xx.h:341
reg_ltdc_lc_t::CKCR
volatile uint32_t CKCR
Definition: reg_stm32f4xx.h:755
reg_dbg_t::APB2_FZ
volatile uint32_t APB2_FZ
Definition: reg_stm32f4xx.h:1935
reg_sdio_t::DCOUNT
volatile uint32_t DCOUNT
Definition: reg_stm32f4xx.h:1621
reg_can_t::TI1R
volatile uint32_t TI1R
Definition: reg_stm32f4xx.h:1674
reg_gpio_t::OSPEEDR
volatile uint32_t OSPEEDR
Definition: reg_stm32f4xx.h:197
reg_can_t::IER
volatile uint32_t IER
Definition: reg_stm32f4xx.h:1665
reg_rcc_t::AHB1ENR
volatile uint32_t AHB1ENR
Definition: reg_stm32f4xx.h:56
reg_dma2d_t
Representation of DMA2D register.
Definition: reg_stm32f4xx.h:439
reg_gpio_t::PUPDR
volatile uint32_t PUPDR
Definition: reg_stm32f4xx.h:198
reg_adc_t::LTR
volatile uint32_t LTR
Definition: reg_stm32f4xx.h:578
reg_spi_t::CR2
volatile uint32_t CR2
Definition: reg_stm32f4xx.h:1356
reg_sai_block_t::DR
volatile uint32_t DR
Definition: reg_stm32f4xx.h:1454
reg_rcc_t::APB2LPENR
volatile uint32_t APB2LPENR
Definition: reg_stm32f4xx.h:68
reg_dcmi_t::CWSTRT
volatile uint32_t CWSTRT
Definition: reg_stm32f4xx.h:718
reg_flash_t::OPTKEYR
volatile uint32_t OPTKEYR
Definition: reg_stm32f4xx.h:100
reg_usart_t
Universal sync./async. receiver transmiter register.
Definition: reg_stm32f4xx.h:1498
reg_cryp_t::K0LR
volatile uint32_t K0LR
Definition: reg_stm32f4xx.h:1081
reg_sdio_t::FIFO
volatile uint32_t FIFO
Definition: reg_stm32f4xx.h:1627
reg_adc_t::JOFR2
volatile uint32_t JOFR2
Definition: reg_stm32f4xx.h:574
reg_fmc_sram_t
Representation of SRAM register (Bank 1).
Definition: reg_stm32f4xx.h:1746
reg_cryp_t::CSGCM6R
volatile uint32_t CSGCM6R
Definition: reg_stm32f4xx.h:1107
reg_dma_t::HISR
volatile uint32_t HISR
Definition: reg_stm32f4xx.h:395
reg_can_t::TDH2R
volatile uint32_t TDH2R
Definition: reg_stm32f4xx.h:1683
reg_rcc_t::PLLSAICFGR
volatile uint32_t PLLSAICFGR
Definition: reg_stm32f4xx.h:75
reg_exti_t
Representation of EXTI register.
Definition: reg_stm32f4xx.h:538
reg_dma2d_t::BGCOLR
volatile uint32_t BGCOLR
Definition: reg_stm32f4xx.h:450
reg_sai_t
Serial audio interface register.
Definition: reg_stm32f4xx.h:1464
reg_cryp_t::K3RR
volatile uint32_t K3RR
Definition: reg_stm32f4xx.h:1088
reg_cryp_t::CSGCM2R
volatile uint32_t CSGCM2R
Definition: reg_stm32f4xx.h:1103
reg_scb_t::SHCSR
volatile uint32_t SHCSR
Definition: reg_stm32f4xx.h:1844
reg_sai_t::BLOCK1
volatile reg_sai_block_t BLOCK1
Definition: reg_stm32f4xx.h:1465
reg_cryp_t::IV1RR
volatile uint32_t IV1RR
Definition: reg_stm32f4xx.h:1092
reg_tim_t::DMAR
volatile uint32_t DMAR
Definition: reg_stm32f4xx.h:844
reg_fmc_sram_t::BTR4
volatile uint32_t BTR4
Definition: reg_stm32f4xx.h:1754
reg_rcc_t::CSR
volatile uint32_t CSR
Definition: reg_stm32f4xx.h:71
reg_ltdc_lc_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:752
reg_nvic_t::ICPR0
volatile uint32_t ICPR0
Definition: reg_stm32f4xx.h:505
reg_dcmi_t::RIS
volatile uint32_t RIS
Definition: reg_stm32f4xx.h:712
reg_dcmi_t::CWSIZE
volatile uint32_t CWSIZE
Definition: reg_stm32f4xx.h:719
reg_can_t::TDL2R
volatile uint32_t TDL2R
Definition: reg_stm32f4xx.h:1682
reg_rcc_t
Representation of RCC register.
Definition: reg_stm32f4xx.h:44
reg_i2c_t::CR2
volatile uint32_t CR2
Definition: reg_stm32f4xx.h:1293
reg_cryp_t::CSGCMCCM1R
volatile uint32_t CSGCMCCM1R
Definition: reg_stm32f4xx.h:1094
reg_dcmi_t::IER
volatile uint32_t IER
Definition: reg_stm32f4xx.h:713
reg_flash_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:102
reg_dcmi_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:710
reg_spi_t
Representation of SPI register.
Definition: reg_stm32f4xx.h:1354
reg_ltdc_t::BCCR
volatile uint32_t BCCR
Definition: reg_stm32f4xx.h:781
reg_rtc_t::DR
volatile uint32_t DR
Definition: reg_stm32f4xx.h:1230
reg_nvic_t::ICPR2
volatile uint32_t ICPR2
Definition: reg_stm32f4xx.h:507
reg_tim_t
Representation of Timer register.
Definition: reg_stm32f4xx.h:824
reg_dac_t::DHR8RD
volatile uint32_t DHR8RD
Definition: reg_stm32f4xx.h:673
reg_usart_t::CR1
volatile uint32_t CR1
Definition: reg_stm32f4xx.h:1502
reg_scb_t::SCR
volatile uint32_t SCR
Definition: reg_stm32f4xx.h:1839
reg_can_t::RF1R
volatile uint32_t RF1R
Definition: reg_stm32f4xx.h:1664
reg_tim_t::CCR3
volatile uint32_t CCR3
Definition: reg_stm32f4xx.h:840
reg_adc_t::JOFR4
volatile uint32_t JOFR4
Definition: reg_stm32f4xx.h:576
reg_tim_t::CCMR1
volatile uint32_t CCMR1
Definition: reg_stm32f4xx.h:831
reg_hash_t::STR
volatile uint32_t STR
Definition: reg_stm32f4xx.h:1180
reg_i2c_t::DR
volatile uint32_t DR
Definition: reg_stm32f4xx.h:1296
reg_fmc_sram_t::BCR4
volatile uint32_t BCR4
Definition: reg_stm32f4xx.h:1753
reg_exti_t::IMR
volatile uint32_t IMR
Definition: reg_stm32f4xx.h:539
reg_exti_t::RTSR
volatile uint32_t RTSR
Definition: reg_stm32f4xx.h:541
reg_rcc_t::AHB1LPENR
volatile uint32_t AHB1LPENR
Definition: reg_stm32f4xx.h:63
reg_i2c_t::SR1
volatile uint32_t SR1
Definition: reg_stm32f4xx.h:1297
reg_scb_t::MMAR
volatile uint32_t MMAR
Definition: reg_stm32f4xx.h:1851
reg_nvic_t::ICER2
volatile uint32_t ICER2
Definition: reg_stm32f4xx.h:499
reg_can_t::RDL1R
volatile uint32_t RDL1R
Definition: reg_stm32f4xx.h:1692
reg_rcc_t::APB2RSTR
volatile uint32_t APB2RSTR
Definition: reg_stm32f4xx.h:54
reg_rtc_t::ALRMAR
volatile uint32_t ALRMAR
Definition: reg_stm32f4xx.h:1236
reg_can_t::RESERVED5
uint32_t RESERVED5
Definition: reg_stm32f4xx.h:1701
reg_i2c_t::CR1
volatile uint32_t CR1
Definition: reg_stm32f4xx.h:1292
reg_adc_t::JOFR3
volatile uint32_t JOFR3
Definition: reg_stm32f4xx.h:575
reg_rcc_t::CIR
volatile uint32_t CIR
Definition: reg_stm32f4xx.h:48
reg_rcc_t::AHB2LPENR
volatile uint32_t AHB2LPENR
Definition: reg_stm32f4xx.h:64
reg_hash_t::HR3
volatile uint32_t HR3
Definition: reg_stm32f4xx.h:1191
reg_iwdg_t::RLR
volatile uint32_t RLR
Definition: reg_stm32f4xx.h:1012
reg_cryp_t::DMACR
volatile uint32_t DMACR
Definition: reg_stm32f4xx.h:1077
reg_fmc_sram_t::BWTR2
volatile uint32_t BWTR2
Definition: reg_stm32f4xx.h:1758
reg_scb_t::SHPR2
volatile uint32_t SHPR2
Definition: reg_stm32f4xx.h:1842
reg_dcmi_t
Representation of DCMI register.
Definition: reg_stm32f4xx.h:709
reg_sai_block_t::SLOTR
volatile uint32_t SLOTR
Definition: reg_stm32f4xx.h:1450
reg_rtc_t::TAFCR
volatile uint32_t TAFCR
Definition: reg_stm32f4xx.h:1245
reg_rtc_t::SSR
volatile uint32_t SSR
Definition: reg_stm32f4xx.h:1239
reg_flash_t
Representation of FLASH register.
Definition: reg_stm32f4xx.h:97
reg_nvic_t::ISPR2
volatile uint32_t ISPR2
Definition: reg_stm32f4xx.h:503
reg_dac_t::DHR12R1
volatile uint32_t DHR12R1
Definition: reg_stm32f4xx.h:665
reg_spi_t::CRCPR
volatile uint32_t CRCPR
Definition: reg_stm32f4xx.h:1359
reg_adc_t::JDR4
volatile uint32_t JDR4
Definition: reg_stm32f4xx.h:586
reg_ltdc_lc_t::PFCR
volatile uint32_t PFCR
Definition: reg_stm32f4xx.h:756
reg_syscfg_t::MEMRMP
volatile uint32_t MEMRMP
Definition: reg_stm32f4xx.h:339
reg_flash_t::KEYR
volatile uint32_t KEYR
Definition: reg_stm32f4xx.h:99
reg_sdio_t::POWER
volatile uint32_t POWER
Definition: reg_stm32f4xx.h:1609
reg_cryp_t::CSGCMCCM4R
volatile uint32_t CSGCMCCM4R
Definition: reg_stm32f4xx.h:1097
reg_dac_t::DHR8R1
volatile uint32_t DHR8R1
Definition: reg_stm32f4xx.h:667
reg_dac_t::DOR1
volatile uint32_t DOR1
Definition: reg_stm32f4xx.h:674
reg_dac_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:663
reg_adc_t::JDR3
volatile uint32_t JDR3
Definition: reg_stm32f4xx.h:585
reg_sdio_t::RESP1
volatile uint32_t RESP1
Definition: reg_stm32f4xx.h:1614
reg_i2c_t::OAR1
volatile uint32_t OAR1
Definition: reg_stm32f4xx.h:1294
reg_rng_t::DR
volatile uint32_t DR
Definition: reg_stm32f4xx.h:1144
reg_dcmi_t::ICR
volatile uint32_t ICR
Definition: reg_stm32f4xx.h:715
reg_dma2d_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:440
reg_stk_t
Representation of STK register.
Definition: reg_stm32f4xx.h:1876
reg_can_t::RESERVED3
uint32_t RESERVED3
Definition: reg_stm32f4xx.h:1697
reg_gpio_t::AFRH
volatile uint32_t AFRH
Definition: reg_stm32f4xx.h:204
reg_tim_t::CNT
volatile uint32_t CNT
Definition: reg_stm32f4xx.h:834
reg_nvic_t::ICER1
volatile uint32_t ICER1
Definition: reg_stm32f4xx.h:498
reg_spi_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:1357
reg_hash_t::HR2
volatile uint32_t HR2
Definition: reg_stm32f4xx.h:1190
reg_scb_t::HFSR
volatile uint32_t HFSR
Definition: reg_stm32f4xx.h:1849
reg_rcc_t::AHB3ENR
volatile uint32_t AHB3ENR
Definition: reg_stm32f4xx.h:58
reg_sai_t::BLOCK2
volatile reg_sai_block_t BLOCK2
Definition: reg_stm32f4xx.h:1466
reg_dac_t::DOR2
volatile uint32_t DOR2
Definition: reg_stm32f4xx.h:675
reg_iwdg_t::KR
volatile uint32_t KR
Definition: reg_stm32f4xx.h:1010
reg_sdio_t::DTIMER
volatile uint32_t DTIMER
Definition: reg_stm32f4xx.h:1618
reg_rng_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:1142
reg_adc_t
Representation of ADC register.
Definition: reg_stm32f4xx.h:567
reg_sdio_t::ARG
volatile uint32_t ARG
Definition: reg_stm32f4xx.h:1611
reg_tim_t::CR2
volatile uint32_t CR2
Definition: reg_stm32f4xx.h:826
reg_adc_t::JDR2
volatile uint32_t JDR2
Definition: reg_stm32f4xx.h:584
reg_sdio_t::DCTRL
volatile uint32_t DCTRL
Definition: reg_stm32f4xx.h:1620
reg_cryp_t::CSGCM0R
volatile uint32_t CSGCM0R
Definition: reg_stm32f4xx.h:1101
reg_dma2d_t::AMTCR
volatile uint32_t AMTCR
Definition: reg_stm32f4xx.h:459
reg_adc_t::JSQR
volatile uint32_t JSQR
Definition: reg_stm32f4xx.h:582
reg_hash_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:1178
reg_wwdg_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:1039
reg_cryp_t::CSGCMCCM7R
volatile uint32_t CSGCMCCM7R
Definition: reg_stm32f4xx.h:1100
reg_dma_stream_t::M1AR
volatile uint32_t M1AR
Definition: reg_stm32f4xx.h:382
reg_rtc_t::BKP18R
volatile uint32_t BKP18R
Definition: reg_stm32f4xx.h:1267
reg_wwdg_t::CFR
volatile uint32_t CFR
Definition: reg_stm32f4xx.h:1038
reg_fmc_sram_t::BTR1
volatile uint32_t BTR1
Definition: reg_stm32f4xx.h:1748
reg_ltdc_t::ICR
volatile uint32_t ICR
Definition: reg_stm32f4xx.h:784
reg_rtc_t::BKP11R
volatile uint32_t BKP11R
Definition: reg_stm32f4xx.h:1260
reg_hash_t::DIN
volatile uint32_t DIN
Definition: reg_stm32f4xx.h:1179
reg_usart_t::BRR
volatile uint32_t BRR
Definition: reg_stm32f4xx.h:1501
reg_dma2d_t::OCOLR
volatile uint32_t OCOLR
Definition: reg_stm32f4xx.h:454
reg_sdio_t::FIFOCNT
volatile uint32_t FIFOCNT
Definition: reg_stm32f4xx.h:1626
reg_dac_t::DHR12L1
volatile uint32_t DHR12L1
Definition: reg_stm32f4xx.h:666
reg_fmc_t::SRAM
reg_fmc_sram_t SRAM
Definition: reg_stm32f4xx.h:1773
reg_gpio_t::LCKR
volatile uint32_t LCKR
Definition: reg_stm32f4xx.h:202
reg_rtc_t::BKP2R
volatile uint32_t BKP2R
Definition: reg_stm32f4xx.h:1251
reg_rtc_t::TR
volatile uint32_t TR
Definition: reg_stm32f4xx.h:1229
reg_rtc_t::ALRMBSSR
volatile uint32_t ALRMBSSR
Definition: reg_stm32f4xx.h:1247
reg_rcc_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:45
reg_adc_t::SQR2
volatile uint32_t SQR2
Definition: reg_stm32f4xx.h:580
reg_cryp_t::DIN
volatile uint32_t DIN
Definition: reg_stm32f4xx.h:1075
reg_hash_t::HR5
volatile uint32_t HR5
Definition: reg_stm32f4xx.h:1193
reg_dac_t::DHR12LD
volatile uint32_t DHR12LD
Definition: reg_stm32f4xx.h:672
reg_dma2d_t::BGCMAR
volatile uint32_t BGCMAR
Definition: reg_stm32f4xx.h:452
reg_rtc_t::CALR
volatile uint32_t CALR
Definition: reg_stm32f4xx.h:1244
reg_hash_t::HR1
volatile uint32_t HR1
Definition: reg_stm32f4xx.h:1189
reg_adc_t::HTR
volatile uint32_t HTR
Definition: reg_stm32f4xx.h:577
reg_can_t::TDL0R
volatile uint32_t TDL0R
Definition: reg_stm32f4xx.h:1672
reg_ltdc_lc_t
Representation of LTDC layer control register.
Definition: reg_stm32f4xx.h:751
reg_dma2d_t::FGCMAR
volatile uint32_t FGCMAR
Definition: reg_stm32f4xx.h:451
reg_cryp_t::IV0RR
volatile uint32_t IV0RR
Definition: reg_stm32f4xx.h:1090
reg_cryp_t::CSGCM3R
volatile uint32_t CSGCM3R
Definition: reg_stm32f4xx.h:1104
reg_nvic_t::IABR1
volatile uint32_t IABR1
Definition: reg_stm32f4xx.h:510
reg_dbg_t::APB1_FZ
volatile uint32_t APB1_FZ
Definition: reg_stm32f4xx.h:1934
reg_rcc_t::APB1ENR
volatile uint32_t APB1ENR
Definition: reg_stm32f4xx.h:60
reg_rtc_t::BKP13R
volatile uint32_t BKP13R
Definition: reg_stm32f4xx.h:1262
reg_can_t::RDL0R
volatile uint32_t RDL0R
Definition: reg_stm32f4xx.h:1687
reg_dma2d_t::BGOR
volatile uint32_t BGOR
Definition: reg_stm32f4xx.h:446
reg_syscfg_t
Representation of SYSCFG register.
Definition: reg_stm32f4xx.h:338
reg_adc_t::JDR1
volatile uint32_t JDR1
Definition: reg_stm32f4xx.h:583
reg_i2c_t::TRISE
volatile uint32_t TRISE
Definition: reg_stm32f4xx.h:1300
reg_fmc_sram_t::BTR3
volatile uint32_t BTR3
Definition: reg_stm32f4xx.h:1752
reg_rtc_t::TSDR
volatile uint32_t TSDR
Definition: reg_stm32f4xx.h:1242
reg_ltdc_lc_t::BFCR
volatile uint32_t BFCR
Definition: reg_stm32f4xx.h:759
reg_crc_t
Representation of CRC register.
Definition: reg_stm32f4xx.h:124
reg_can_t::TDH1R
volatile uint32_t TDH1R
Definition: reg_stm32f4xx.h:1678
reg_usart_t::CR3
volatile uint32_t CR3
Definition: reg_stm32f4xx.h:1504
reg_spi_t::DR
volatile uint32_t DR
Definition: reg_stm32f4xx.h:1358
reg_ltdc_t::CPSR
volatile uint32_t CPSR
Definition: reg_stm32f4xx.h:786
reg_syscfg_t::PMC
volatile uint32_t PMC
Definition: reg_stm32f4xx.h:340
reg_can_t::TDH0R
volatile uint32_t TDH0R
Definition: reg_stm32f4xx.h:1673
reg_adccom_t::CDR
volatile uint32_t CDR
Definition: reg_stm32f4xx.h:639
reg_rcc_t::SSCGR
volatile uint32_t SSCGR
Definition: reg_stm32f4xx.h:73
reg_ltdc_t::SSCR
volatile uint32_t SSCR
Definition: reg_stm32f4xx.h:775
reg_tim_t::PSC
volatile uint32_t PSC
Definition: reg_stm32f4xx.h:835
reg_dcmi_t::ESCR
volatile uint32_t ESCR
Definition: reg_stm32f4xx.h:716
reg_fpu_t::FPCCR
volatile uint32_t FPCCR
Definition: reg_stm32f4xx.h:1906
reg_wwdg_t
Definition: reg_stm32f4xx.h:1036
reg_can_t::TDT1R
volatile uint32_t TDT1R
Definition: reg_stm32f4xx.h:1675
reg_rcc_t::AHB1RSTR
volatile uint32_t AHB1RSTR
Definition: reg_stm32f4xx.h:49
reg_pwr_t::CSR
volatile uint32_t CSR
Definition: reg_stm32f4xx.h:162
reg_rcc_t::APB2ENR
volatile uint32_t APB2ENR
Definition: reg_stm32f4xx.h:61
reg_dma2d_t::OPFCCR
volatile uint32_t OPFCCR
Definition: reg_stm32f4xx.h:453
reg_hash_t::HR6
volatile uint32_t HR6
Definition: reg_stm32f4xx.h:1194
reg_sdio_t::ICR
volatile uint32_t ICR
Definition: reg_stm32f4xx.h:1623
reg_dac_t
Representation of DAC register.
Definition: reg_stm32f4xx.h:662
reg_dma_t::LISR
volatile uint32_t LISR
Definition: reg_stm32f4xx.h:394
reg_sdio_t::RESP2
volatile uint32_t RESP2
Definition: reg_stm32f4xx.h:1615
reg_syscfg_t::EXTICR3
volatile uint32_t EXTICR3
Definition: reg_stm32f4xx.h:343
reg_adc_t::SMPR2
volatile uint32_t SMPR2
Definition: reg_stm32f4xx.h:572
reg_can_t::TSR
volatile uint32_t TSR
Definition: reg_stm32f4xx.h:1662
reg_gpio_t::IDR
volatile uint32_t IDR
Definition: reg_stm32f4xx.h:199
reg_scb_t::ICSR
volatile uint32_t ICSR
Definition: reg_stm32f4xx.h:1836
reg_sai_block_t
Serial audio interface subblock register.
Definition: reg_stm32f4xx.h:1446
reg_rtc_t::BKP12R
volatile uint32_t BKP12R
Definition: reg_stm32f4xx.h:1261
reg_mpu_t::RNR
volatile uint32_t RNR
Definition: reg_stm32f4xx.h:1809
reg_adc_t::CR2
volatile uint32_t CR2
Definition: reg_stm32f4xx.h:570
reg_ltdc_lc_t::CLUTWR
volatile uint32_t CLUTWR
Definition: reg_stm32f4xx.h:763
reg_stk_t::VAL
volatile uint32_t VAL
Definition: reg_stm32f4xx.h:1879
reg_dma_t::HIFCR
volatile uint32_t HIFCR
Definition: reg_stm32f4xx.h:397
reg_cryp_t::K0RR
volatile uint32_t K0RR
Definition: reg_stm32f4xx.h:1082
reg_ltdc_lc_t::CFBLR
volatile uint32_t CFBLR
Definition: reg_stm32f4xx.h:761
reg_cryp_t::CSGCMCCM3R
volatile uint32_t CSGCMCCM3R
Definition: reg_stm32f4xx.h:1096
reg_can_t::RF0R
volatile uint32_t RF0R
Definition: reg_stm32f4xx.h:1663
reg_dma_stream_t::FCR
volatile uint32_t FCR
Definition: reg_stm32f4xx.h:383
reg_rtc_t::BKP6R
volatile uint32_t BKP6R
Definition: reg_stm32f4xx.h:1255
reg_sai_block_t::IM
volatile uint32_t IM
Definition: reg_stm32f4xx.h:1451
reg_fmc_sram_t::BWTR1
volatile uint32_t BWTR1
Definition: reg_stm32f4xx.h:1756
reg_rtc_t::BKP4R
volatile uint32_t BKP4R
Definition: reg_stm32f4xx.h:1253
reg_i2c_t
Representation of I2C register.
Definition: reg_stm32f4xx.h:1291
reg_cryp_t::K1RR
volatile uint32_t K1RR
Definition: reg_stm32f4xx.h:1084
reg_cryp_t::CSGCM1R
volatile uint32_t CSGCM1R
Definition: reg_stm32f4xx.h:1102
reg_dbg_t
Representation of DBG register.
Definition: reg_stm32f4xx.h:1931
reg_can_t::RI1R
volatile uint32_t RI1R
Definition: reg_stm32f4xx.h:1689
reg_cryp_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:1073
reg_ltdc_lc_t::DCCR
volatile uint32_t DCCR
Definition: reg_stm32f4xx.h:758
reg_ltdc_t::LAYER2
reg_ltdc_lc_t LAYER2
Definition: reg_stm32f4xx.h:791
reg_scb_t::AIRCR
volatile uint32_t AIRCR
Definition: reg_stm32f4xx.h:1838
reg_rtc_t::TSSSR
volatile uint32_t TSSSR
Definition: reg_stm32f4xx.h:1243
reg_can_t::RDH0R
volatile uint32_t RDH0R
Definition: reg_stm32f4xx.h:1688
reg_tim_t::CCR4
volatile uint32_t CCR4
Definition: reg_stm32f4xx.h:841
reg_scb_t::SHPR1
volatile uint32_t SHPR1
Definition: reg_stm32f4xx.h:1841
reg_rcc_t::APB1LPENR
volatile uint32_t APB1LPENR
Definition: reg_stm32f4xx.h:67
reg_iwdg_t
Representation of IWDG register.
Definition: reg_stm32f4xx.h:1009
reg_rtc_t::ISR
volatile uint32_t ISR
Definition: reg_stm32f4xx.h:1232
reg_dma2d_t::FGPFCCR
volatile uint32_t FGPFCCR
Definition: reg_stm32f4xx.h:447
reg_scb_t
Representation of SCB register.
Definition: reg_stm32f4xx.h:1834
reg_nvic_t::IABR2
volatile uint32_t IABR2
Definition: reg_stm32f4xx.h:511
reg_cryp_t::IMSCR
volatile uint32_t IMSCR
Definition: reg_stm32f4xx.h:1078
reg_gpio_t::MODER
volatile uint32_t MODER
Definition: reg_stm32f4xx.h:195
reg_nvic_t::ISER1
volatile uint32_t ISER1
Definition: reg_stm32f4xx.h:494
reg_rtc_t::BKP8R
volatile uint32_t BKP8R
Definition: reg_stm32f4xx.h:1257
reg_can_t::TI2R
volatile uint32_t TI2R
Definition: reg_stm32f4xx.h:1679
reg_dma2d_t::FGMAR
volatile uint32_t FGMAR
Definition: reg_stm32f4xx.h:443
reg_ltdc_lc_t::CFBLNR
volatile uint32_t CFBLNR
Definition: reg_stm32f4xx.h:762
reg_dma2d_t::NLR
volatile uint32_t NLR
Definition: reg_stm32f4xx.h:457
reg_syscfg_t::CMPCR
volatile uint32_t CMPCR
Definition: reg_stm32f4xx.h:346
reg_ltdc_t::IER
volatile uint32_t IER
Definition: reg_stm32f4xx.h:782
reg_i2c_t::SR2
volatile uint32_t SR2
Definition: reg_stm32f4xx.h:1298
reg_rng_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:1143
reg_spi_t::CR1
volatile uint32_t CR1
Definition: reg_stm32f4xx.h:1355
reg_ltdc_t::AWCR
volatile uint32_t AWCR
Definition: reg_stm32f4xx.h:777
reg_ltdc_lc_t::CFBAR
volatile uint32_t CFBAR
Definition: reg_stm32f4xx.h:760
reg_sai_block_t::CR2
volatile uint32_t CR2
Definition: reg_stm32f4xx.h:1448
reg_rtc_t::BKP7R
volatile uint32_t BKP7R
Definition: reg_stm32f4xx.h:1256
reg_spi_t::TXCRCR
volatile uint32_t TXCRCR
Definition: reg_stm32f4xx.h:1361
reg_ltdc_t::LAYER1
reg_ltdc_lc_t LAYER1
Definition: reg_stm32f4xx.h:789
reg_cryp_t::CSGCMCCM0R
volatile uint32_t CSGCMCCM0R
Definition: reg_stm32f4xx.h:1093
reg_nvic_t::ISER0
volatile uint32_t ISER0
Definition: reg_stm32f4xx.h:493
reg_mpu_t::RBAR
volatile uint32_t RBAR
Definition: reg_stm32f4xx.h:1810
reg_ltdc_t::GCR
volatile uint32_t GCR
Definition: reg_stm32f4xx.h:779
reg_rcc_t::CFGR
volatile uint32_t CFGR
Definition: reg_stm32f4xx.h:47
reg_fpu_t::CPACR
volatile uint32_t CPACR
Definition: reg_stm32f4xx.h:1904
reg_cryp_t::K2RR
volatile uint32_t K2RR
Definition: reg_stm32f4xx.h:1086
reg_scb_t::SHPR3
volatile uint32_t SHPR3
Definition: reg_stm32f4xx.h:1843
reg_flash_t::OPTCR1
volatile uint32_t OPTCR1
Definition: reg_stm32f4xx.h:104
reg_adccom_t::CSR
volatile uint32_t CSR
Definition: reg_stm32f4xx.h:637
reg_rcc_t::DCKCFGR
volatile uint32_t DCKCFGR
Definition: reg_stm32f4xx.h:76
reg_tim_t::CCMR2
volatile uint32_t CCMR2
Definition: reg_stm32f4xx.h:832
reg_adc_t::SQR1
volatile uint32_t SQR1
Definition: reg_stm32f4xx.h:579
reg_can_t::BTR
volatile uint32_t BTR
Definition: reg_stm32f4xx.h:1667
reg_dbg_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:1933
reg_iwdg_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:1013
reg_scb_t::CFSR
volatile uint32_t CFSR
Definition: reg_stm32f4xx.h:1845
reg_adccom_t
Representation of ADC common register.
Definition: reg_stm32f4xx.h:636
reg_adc_t::JOFR1
volatile uint32_t JOFR1
Definition: reg_stm32f4xx.h:573
reg_rtc_t::BKP3R
volatile uint32_t BKP3R
Definition: reg_stm32f4xx.h:1252
reg_adc_t::SMPR1
volatile uint32_t SMPR1
Definition: reg_stm32f4xx.h:571
reg_sdio_t::RESP3
volatile uint32_t RESP3
Definition: reg_stm32f4xx.h:1616
reg_sdio_t
Representation of SDIO register.
Definition: reg_stm32f4xx.h:1608
reg_rcc_t::AHB2RSTR
volatile uint32_t AHB2RSTR
Definition: reg_stm32f4xx.h:50
reg_gpio_t::BSRR
volatile uint32_t BSRR
Definition: reg_stm32f4xx.h:201
reg_cryp_t::IV0LR
volatile uint32_t IV0LR
Definition: reg_stm32f4xx.h:1089
reg_rtc_t::WUTR
volatile uint32_t WUTR
Definition: reg_stm32f4xx.h:1234
reg_fmc_sram_t::BCR2
volatile uint32_t BCR2
Definition: reg_stm32f4xx.h:1749
reg_sdio_t::RESPCMD
volatile uint32_t RESPCMD
Definition: reg_stm32f4xx.h:1613
reg_tim_t::CCER
volatile uint32_t CCER
Definition: reg_stm32f4xx.h:833
reg_dcmi_t::MIS
volatile uint32_t MIS
Definition: reg_stm32f4xx.h:714
reg_fmc_t
Representation of FMC register.
Definition: reg_stm32f4xx.h:1772
reg_rtc_t::WPR
volatile uint32_t WPR
Definition: reg_stm32f4xx.h:1238
reg_usart_t::GPTR
volatile uint32_t GPTR
Definition: reg_stm32f4xx.h:1505
reg_mpu_t::RASR
volatile uint32_t RASR
Definition: reg_stm32f4xx.h:1811
reg_rcc_t::PLLCFGR
volatile uint32_t PLLCFGR
Definition: reg_stm32f4xx.h:46
reg_dac_t::SWTRIGR
volatile uint32_t SWTRIGR
Definition: reg_stm32f4xx.h:664
reg_cryp_t
Representation of CRYP register.
Definition: reg_stm32f4xx.h:1072
reg_cryp_t::CSGCM7R
volatile uint32_t CSGCM7R
Definition: reg_stm32f4xx.h:1108
reg_nvic_t::ICER0
volatile uint32_t ICER0
Definition: reg_stm32f4xx.h:497
reg_can_t::RDT1R
volatile uint32_t RDT1R
Definition: reg_stm32f4xx.h:1690
reg_cryp_t::CSGCM4R
volatile uint32_t CSGCM4R
Definition: reg_stm32f4xx.h:1105
reg_rcc_t::AHB3LPENR
volatile uint32_t AHB3LPENR
Definition: reg_stm32f4xx.h:65
reg_sdio_t::CMD
volatile uint32_t CMD
Definition: reg_stm32f4xx.h:1612
reg_usart_t::CR2
volatile uint32_t CR2
Definition: reg_stm32f4xx.h:1503
reg_rtc_t::PRER
volatile uint32_t PRER
Definition: reg_stm32f4xx.h:1233
reg_tim_t::RCR
volatile uint32_t RCR
Definition: reg_stm32f4xx.h:837
reg_cryp_t::CSGCMCCM5R
volatile uint32_t CSGCMCCM5R
Definition: reg_stm32f4xx.h:1098
reg_ltdc_t
Representation of LTDC register.
Definition: reg_stm32f4xx.h:773
reg_dma2d_t::OOR
volatile uint32_t OOR
Definition: reg_stm32f4xx.h:456
reg_can_t::ESR
volatile uint32_t ESR
Definition: reg_stm32f4xx.h:1666
reg_tim_t::DIER
volatile uint32_t DIER
Definition: reg_stm32f4xx.h:828
reg_rtc_t::BKP1R
volatile uint32_t BKP1R
Definition: reg_stm32f4xx.h:1250
reg_gpio_t::AFRL
volatile uint32_t AFRL
Definition: reg_stm32f4xx.h:203
reg_dma2d_t::IFCR
volatile uint32_t IFCR
Definition: reg_stm32f4xx.h:442
reg_can_t
Representation of CAN register.
Definition: reg_stm32f4xx.h:1659
reg_dma_t::LIFCR
volatile uint32_t LIFCR
Definition: reg_stm32f4xx.h:396
reg_fmc_sram_t::BWTR3
volatile uint32_t BWTR3
Definition: reg_stm32f4xx.h:1760
reg_rtc_t::BKP9R
volatile uint32_t BKP9R
Definition: reg_stm32f4xx.h:1258
reg_fmc_sram_t::BCR1
volatile uint32_t BCR1
Definition: reg_stm32f4xx.h:1747
reg_hash_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:1184
reg_cryp_t::IV1LR
volatile uint32_t IV1LR
Definition: reg_stm32f4xx.h:1091
reg_fpu_t::FPCAR
volatile uint32_t FPCAR
Definition: reg_stm32f4xx.h:1907
reg_sdio_t::STA
volatile uint32_t STA
Definition: reg_stm32f4xx.h:1622
reg_tim_t::CCR2
volatile uint32_t CCR2
Definition: reg_stm32f4xx.h:839
reg_gpio_t
Representation of GPIO register.
Definition: reg_stm32f4xx.h:194
reg_rtc_t::CALIBR
volatile uint32_t CALIBR
Definition: reg_stm32f4xx.h:1235
reg_cryp_t::K3LR
volatile uint32_t K3LR
Definition: reg_stm32f4xx.h:1087
reg_scb_t::AFSR
volatile uint32_t AFSR
Definition: reg_stm32f4xx.h:1853
reg_fmc_sram_t::BWTR4
volatile uint32_t BWTR4
Definition: reg_stm32f4xx.h:1762
reg_dcmi_t::DR
volatile uint32_t DR
Definition: reg_stm32f4xx.h:720
reg_scb_t::VTOR
volatile uint32_t VTOR
Definition: reg_stm32f4xx.h:1837
reg_rng_t
Representation of RNG register.
Definition: reg_stm32f4xx.h:1141
reg_cryp_t::CSGCMCCM2R
volatile uint32_t CSGCMCCM2R
Definition: reg_stm32f4xx.h:1095
reg_adc_t::CR1
volatile uint32_t CR1
Definition: reg_stm32f4xx.h:569
reg_tim_t::BDTR
volatile uint32_t BDTR
Definition: reg_stm32f4xx.h:842
reg_exti_t::FTSR
volatile uint32_t FTSR
Definition: reg_stm32f4xx.h:542
reg_adc_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:568
reg_rtc_t::BKP5R
volatile uint32_t BKP5R
Definition: reg_stm32f4xx.h:1254
reg_dma_stream_t::CR
volatile uint32_t CR
Definition: reg_stm32f4xx.h:378
reg_nvic_t::ISPR0
volatile uint32_t ISPR0
Definition: reg_stm32f4xx.h:501
reg_rtc_t::BKP14R
volatile uint32_t BKP14R
Definition: reg_stm32f4xx.h:1263
reg_crc_t::IDR
volatile uint32_t IDR
Definition: reg_stm32f4xx.h:126
reg_adccom_t::CCR
volatile uint32_t CCR
Definition: reg_stm32f4xx.h:638
reg_scb_t::CPUID
volatile uint32_t CPUID
Definition: reg_stm32f4xx.h:1835
reg_dma2d_t::BGMAR
volatile uint32_t BGMAR
Definition: reg_stm32f4xx.h:445
reg_cryp_t::CSGCM5R
volatile uint32_t CSGCM5R
Definition: reg_stm32f4xx.h:1106
reg_spi_t::I2SPR
volatile uint32_t I2SPR
Definition: reg_stm32f4xx.h:1363
reg_ltdc_lc_t::WVPCR
volatile uint32_t WVPCR
Definition: reg_stm32f4xx.h:754
reg_fmc_sram_t::BTR2
volatile uint32_t BTR2
Definition: reg_stm32f4xx.h:1750
reg_ltdc_t::ISR
volatile uint32_t ISR
Definition: reg_stm32f4xx.h:783
reg_i2c_t::OAR2
volatile uint32_t OAR2
Definition: reg_stm32f4xx.h:1295
reg_sdio_t::MASK
volatile uint32_t MASK
Definition: reg_stm32f4xx.h:1624
reg_adc_t::DR
volatile uint32_t DR
Definition: reg_stm32f4xx.h:587
reg_cryp_t::DOUT
volatile uint32_t DOUT
Definition: reg_stm32f4xx.h:1076
reg_sdio_t::RESP4
volatile uint32_t RESP4
Definition: reg_stm32f4xx.h:1617
reg_dma2d_t::OMAR
volatile uint32_t OMAR
Definition: reg_stm32f4xx.h:455
reg_dma_stream_t::NDTR
volatile uint32_t NDTR
Definition: reg_stm32f4xx.h:379
reg_rtc_t::ALRMBR
volatile uint32_t ALRMBR
Definition: reg_stm32f4xx.h:1237
reg_exti_t::PR
volatile uint32_t PR
Definition: reg_stm32f4xx.h:544
reg_i2c_t::FLTR
volatile uint32_t FLTR
Definition: reg_stm32f4xx.h:1301
reg_dac_t::DHR8R2
volatile uint32_t DHR8R2
Definition: reg_stm32f4xx.h:670
reg_sai_block_t::FRCR
volatile uint32_t FRCR
Definition: reg_stm32f4xx.h:1449
reg_ltdc_t::LIPCR
volatile uint32_t LIPCR
Definition: reg_stm32f4xx.h:785
reg_can_t::TDT0R
volatile uint32_t TDT0R
Definition: reg_stm32f4xx.h:1670
reg_cryp_t::SR
volatile uint32_t SR
Definition: reg_stm32f4xx.h:1074
reg_rtc_t::TSTR
volatile uint32_t TSTR
Definition: reg_stm32f4xx.h:1241
reg_nvic_t::ISER2
volatile uint32_t ISER2
Definition: reg_stm32f4xx.h:495
reg_can_t::RDH1R
volatile uint32_t RDH1R
Definition: reg_stm32f4xx.h:1693
reg_rtc_t::ALRMASSR
volatile uint32_t ALRMASSR
Definition: reg_stm32f4xx.h:1246
reg_mpu_t
Representation of MPU register.
Definition: reg_stm32f4xx.h:1806
reg_ltdc_t::TWCR
volatile uint32_t TWCR
Definition: reg_stm32f4xx.h:778
reg_rtc_t
Representation of RTC register.
Definition: reg_stm32f4xx.h:1228
reg_dma2d_t::ISR
volatile uint32_t ISR
Definition: reg_stm32f4xx.h:441
reg_tim_t::OR
volatile uint32_t OR
Definition: reg_stm32f4xx.h:845
reg_spi_t::I2SCFGR
volatile uint32_t I2SCFGR
Definition: reg_stm32f4xx.h:1362
reg_dma_t
Representation of DMA register.
Definition: reg_stm32f4xx.h:393
reg_cryp_t::K1LR
volatile uint32_t K1LR
Definition: reg_stm32f4xx.h:1083
reg_adc_t::SQR3
volatile uint32_t SQR3
Definition: reg_stm32f4xx.h:581
reg_can_t::RESERVED4
uint32_t RESERVED4
Definition: reg_stm32f4xx.h:1699
reg_ltdc_lc_t::WHPCR
volatile uint32_t WHPCR
Definition: reg_stm32f4xx.h:753
reg_can_t::RI0R
volatile uint32_t RI0R
Definition: reg_stm32f4xx.h:1684
reg_syscfg_t::EXTICR4
volatile uint32_t EXTICR4
Definition: reg_stm32f4xx.h:344
reg_nvic_t::ISPR1
volatile uint32_t ISPR1
Definition: reg_stm32f4xx.h:502
reg_cryp_t::CSGCMCCM6R
volatile uint32_t CSGCMCCM6R
Definition: reg_stm32f4xx.h:1099
reg_nvic_t
Representation of NVIC register.
Definition: reg_stm32f4xx.h:492
reg_tim_t::ARR
volatile uint32_t ARR
Definition: reg_stm32f4xx.h:836
reg_nvic_t::STIR
volatile uint32_t STIR
Definition: reg_stm32f4xx.h:516
reg_pwr_t
Representation of PWR register.
Definition: reg_stm32f4xx.h:160
reg_rtc_t::BKP0R
volatile uint32_t BKP0R
Definition: reg_stm32f4xx.h:1249
reg_fmc_sram_t::BCR3
volatile uint32_t BCR3
Definition: reg_stm32f4xx.h:1751
reg_can_t::MSR
volatile uint32_t MSR
Definition: reg_stm32f4xx.h:1661
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