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InES Hardware Abstraction Layer
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Registries for STM32F4xx. More...
#include <stdint.h>Go to the source code of this file.
Data Structures | |
| struct | reg_rcc_t |
| Representation of RCC register. More... | |
| struct | reg_flash_t |
| Representation of FLASH register. More... | |
| struct | reg_crc_t |
| Representation of CRC register. More... | |
| struct | reg_pwr_t |
| Representation of PWR register. More... | |
| struct | reg_gpio_t |
| Representation of GPIO register. More... | |
| struct | reg_syscfg_t |
| Representation of SYSCFG register. More... | |
| struct | reg_dma_stream_t |
| Representation of DMA stream register. More... | |
| struct | reg_dma_t |
| Representation of DMA register. More... | |
| struct | reg_dma2d_t |
| Representation of DMA2D register. More... | |
| struct | reg_nvic_t |
| Representation of NVIC register. More... | |
| struct | reg_exti_t |
| Representation of EXTI register. More... | |
| struct | reg_adc_t |
| Representation of ADC register. More... | |
| struct | reg_adccom_t |
| Representation of ADC common register. More... | |
| struct | reg_dac_t |
| Representation of DAC register. More... | |
| struct | reg_dcmi_t |
| Representation of DCMI register. More... | |
| struct | reg_ltdc_lc_t |
| Representation of LTDC layer control register. More... | |
| struct | reg_ltdc_t |
| Representation of LTDC register. More... | |
| struct | reg_tim_t |
| Representation of Timer register. More... | |
| struct | reg_iwdg_t |
| Representation of IWDG register. More... | |
| struct | reg_wwdg_t |
| struct | reg_cryp_t |
| Representation of CRYP register. More... | |
| struct | reg_rng_t |
| Representation of RNG register. More... | |
| struct | reg_hash_t |
| Representation of HASH register. More... | |
| struct | reg_rtc_t |
| Representation of RTC register. More... | |
| struct | reg_i2c_t |
| Representation of I2C register. More... | |
| struct | reg_spi_t |
| Representation of SPI register. More... | |
| struct | reg_sai_block_t |
| Serial audio interface subblock register. More... | |
| struct | reg_sai_t |
| Serial audio interface register. More... | |
| struct | reg_usart_t |
| Universal sync./async. receiver transmiter register. More... | |
| struct | reg_sdio_t |
| Representation of SDIO register. More... | |
| struct | reg_can_t |
| Representation of CAN register. More... | |
| struct | reg_fmc_sram_t |
| Representation of SRAM register (Bank 1). More... | |
| struct | reg_fmc_t |
| Representation of FMC register. More... | |
| struct | reg_mpu_t |
| Representation of MPU register. More... | |
| struct | reg_scb_t |
| Representation of SCB register. More... | |
| struct | reg_stk_t |
| Representation of STK register. More... | |
| struct | reg_fpu_t |
| Representation of FPU register. More... | |
| struct | reg_dbg_t |
| Representation of DBG register. More... | |
Macros | |
| #define | REG_SET(REG, BIT) ( (REG) |= (BIT) ) |
| #define | REG_CLR(REG, BIT) ( (REG) &= ~(BIT) ) |
| #define | REG_TGL(REG, BIT) |
| #define | RCC ( (reg_rcc_t *) 0x40023800 ) |
| #define | FLASH ( (reg_flash_t *) 0x40023c00 ) |
| #define | CRC ( (reg_crc_t *) 0x40023000 ) |
| #define | CRC_RCC_PATTERN ( 0x1 << 12u ) |
| #define | CRC_RESET() REG_TGL(RCC->AHB1RSTR, CRC_RCC_PATTERN) |
| #define | CRC_ENABLE() REG_SET(RCC->AHB1ENR, CRC_RCC_PATTERN) |
| #define | CRC_DISABLE() REG_CLR(RCC->AHB1ENR, CRC_RCC_PATTERN) |
| #define | CRC_LP_ENABLE() REG_SET(RCC->AHB1LPENR, CRC_RCC_PATTERN) |
| #define | CRC_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, CRC_RCC_PATTERN) |
| #define | PWR ( (reg_pwr_t *) 0x40007000 ) |
| #define | PWR_RCC_PATTERN ( 0x1 << 28u ) |
| #define | PWR_RESET() REG_TGL(RCC->APB1RSTR, PWR_RCC_PATTERN) |
| #define | PWR_ENABLE() REG_SET(RCC->APB1ENR, PWR_RCC_PATTERN) |
| #define | PWR_DISABLE() REG_CLR(RCC->APB1ENR, PWR_RCC_PATTERN) |
| #define | PWR_LP_ENABLE() REG_SET(RCC->APB1LPENR, PWR_RCC_PATTERN) |
| #define | PWR_LP_DISABLE() REG_CLR(RCC->APB1LPENR, PWR_RCC_PATTERN) |
| #define | GPIOA ( (reg_gpio_t *) 0x40020000 ) |
| #define | GPIOB ( (reg_gpio_t *) 0x40020400 ) |
| #define | GPIOC ( (reg_gpio_t *) 0x40020800 ) |
| #define | GPIOD ( (reg_gpio_t *) 0x40020c00 ) |
| #define | GPIOE ( (reg_gpio_t *) 0x40021000 ) |
| #define | GPIOF ( (reg_gpio_t *) 0x40021400 ) |
| #define | GPIOG ( (reg_gpio_t *) 0x40021800 ) |
| #define | GPIOH ( (reg_gpio_t *) 0x40021c00 ) |
| #define | GPIOI ( (reg_gpio_t *) 0x40022000 ) |
| #define | GPIOJ ( (reg_gpio_t *) 0x40022400 ) |
| #define | GPIOK ( (reg_gpio_t *) 0x40022800 ) |
| #define | GPIOA_RCC_PATTERN ( 0x1 << 0u ) |
| #define | GPIOA_RESET() REG_TGL(RCC->AHB1RSTR, GPIOA_RCC_PATTERN) |
| #define | GPIOA_ENABLE() REG_SET(RCC->AHB1ENR, GPIOA_RCC_PATTERN) |
| #define | GPIOA_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOA_RCC_PATTERN) |
| #define | GPIOA_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOA_RCC_PATTERN) |
| #define | GPIOA_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOA_RCC_PATTERN) |
| #define | GPIOB_RCC_PATTERN ( 0x1 << 1u ) |
| #define | GPIOB_RESET() REG_TGL(RCC->AHB1RSTR, GPIOB_RCC_PATTERN) |
| #define | GPIOB_ENABLE() REG_SET(RCC->AHB1ENR, GPIOB_RCC_PATTERN) |
| #define | GPIOB_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOB_RCC_PATTERN) |
| #define | GPIOB_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOB_RCC_PATTERN) |
| #define | GPIOB_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOB_RCC_PATTERN) |
| #define | GPIOC_RCC_PATTERN ( 0x1 << 2u ) |
| #define | GPIOC_RESET() REG_TGL(RCC->AHB1RSTR, GPIOC_RCC_PATTERN) |
| #define | GPIOC_ENABLE() REG_SET(RCC->AHB1ENR, GPIOC_RCC_PATTERN) |
| #define | GPIOC_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOC_RCC_PATTERN) |
| #define | GPIOC_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOC_RCC_PATTERN) |
| #define | GPIOC_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOC_RCC_PATTERN) |
| #define | GPIOD_RCC_PATTERN ( 0x1 << 3u ) |
| #define | GPIOD_RESET() REG_TGL(RCC->AHB1RSTR, GPIOD_RCC_PATTERN) |
| #define | GPIOD_ENABLE() REG_SET(RCC->AHB1ENR, GPIOD_RCC_PATTERN) |
| #define | GPIOD_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOD_RCC_PATTERN) |
| #define | GPIOD_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOD_RCC_PATTERN) |
| #define | GPIOD_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOD_RCC_PATTERN) |
| #define | GPIOE_RCC_PATTERN ( 0x1 << 4u ) |
| #define | GPIOE_RESET() REG_TGL(RCC->AHB1RSTR, GPIOE_RCC_PATTERN) |
| #define | GPIOE_ENABLE() REG_SET(RCC->AHB1ENR, GPIOE_RCC_PATTERN) |
| #define | GPIOE_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOE_RCC_PATTERN) |
| #define | GPIOE_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOE_RCC_PATTERN) |
| #define | GPIOE_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOE_RCC_PATTERN) |
| #define | GPIOF_RCC_PATTERN ( 0x1 << 5u ) |
| #define | GPIOF_RESET() REG_TGL(RCC->AHB1RSTR, GPIOF_RCC_PATTERN) |
| #define | GPIOF_ENABLE() REG_SET(RCC->AHB1ENR, GPIOF_RCC_PATTERN) |
| #define | GPIOF_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOF_RCC_PATTERN) |
| #define | GPIOF_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOF_RCC_PATTERN) |
| #define | GPIOF_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOF_RCC_PATTERN) |
| #define | GPIOG_RCC_PATTERN ( 0x1 << 6u ) |
| #define | GPIOG_RESET() REG_TGL(RCC->AHB1RSTR, GPIOG_RCC_PATTERN) |
| #define | GPIOG_ENABLE() REG_SET(RCC->AHB1ENR, GPIOG_RCC_PATTERN) |
| #define | GPIOG_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOG_RCC_PATTERN) |
| #define | GPIOG_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOG_RCC_PATTERN) |
| #define | GPIOG_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOG_RCC_PATTERN) |
| #define | GPIOH_RCC_PATTERN ( 0x1 << 7u ) |
| #define | GPIOH_RESET() REG_TGL(RCC->AHB1RSTR, GPIOH_RCC_PATTERN) |
| #define | GPIOH_ENABLE() REG_SET(RCC->AHB1ENR, GPIOH_RCC_PATTERN) |
| #define | GPIOH_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOH_RCC_PATTERN) |
| #define | GPIOH_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOH_RCC_PATTERN) |
| #define | GPIOH_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOH_RCC_PATTERN) |
| #define | GPIOI_RCC_PATTERN ( 0x1 << 8u ) |
| #define | GPIOI_RESET() REG_TGL(RCC->AHB1RSTR, GPIOI_RCC_PATTERN) |
| #define | GPIOI_ENABLE() REG_SET(RCC->AHB1ENR, GPIOI_RCC_PATTERN) |
| #define | GPIOI_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOI_RCC_PATTERN) |
| #define | GPIOI_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOI_RCC_PATTERN) |
| #define | GPIOI_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOI_RCC_PATTERN) |
| #define | GPIOJ_RCC_PATTERN ( 0x1 << 9u ) |
| #define | GPIOJ_RESET() REG_TGL(RCC->AHB1RSTR, GPIOJ_RCC_PATTERN) |
| #define | GPIOJ_ENABLE() REG_SET(RCC->AHB1ENR, GPIOJ_RCC_PATTERN) |
| #define | GPIOJ_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOJ_RCC_PATTERN) |
| #define | GPIOJ_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOJ_RCC_PATTERN) |
| #define | GPIOJ_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOJ_RCC_PATTERN) |
| #define | GPIOK_RCC_PATTERN ( 0x1 << 10u ) |
| #define | GPIOK_RESET() REG_TGL(RCC->AHB1RSTR, GPIOK_RCC_PATTERN) |
| #define | GPIOK_ENABLE() REG_SET(RCC->AHB1ENR, GPIOK_RCC_PATTERN) |
| #define | GPIOK_DISABLE() REG_CLR(RCC->AHB1ENR, GPIOK_RCC_PATTERN) |
| #define | GPIOK_LP_ENABLE() REG_SET(RCC->AHB1LPENR, GPIOK_RCC_PATTERN) |
| #define | GPIOK_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, GPIOK_RCC_PATTERN) |
| #define | SYSCFG ( (reg_syscfg_t *) 0x40013800 ) |
| #define | SYSCFG_RCC_PATTERN ( 0x1 << 14u ) |
| #define | SYSCFG_RESET() REG_TGL(RCC->APB2RSTR, SYSCFG_RCC_PATTERN) |
| #define | SYSCFG_ENABLE() REG_SET(RCC->APB2ENR, SYSCFG_RCC_PATTERN) |
| #define | SYSCFG_DISABLE() REG_CLR(RCC->APB2ENR, SYSCFG_RCC_PATTERN) |
| #define | SYSCFG_LP_ENABLE() REG_SET(RCC->APB2LPENR, SYSCFG_RCC_PATTERN) |
| #define | SYSCFG_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SYSCFG_RCC_PATTERN) |
| #define | DMA1 ( (reg_dma_t *) 0x40026000 ) |
| #define | DMA2 ( (reg_dma_t *) 0x40026400 ) |
| #define | DMA1_RCC_PATTERN ( 0x1 << 21u ) |
| #define | DMA1_RESET() REG_TGL(RCC->AHB1RSTR, DMA1_RCC_PATTERN) |
| #define | DMA1_ENABLE() REG_SET(RCC->AHB1ENR, DMA1_RCC_PATTERN) |
| #define | DMA1_DISABLE() REG_CLR(RCC->AHB1ENR, DMA1_RCC_PATTERN) |
| #define | DMA1_LP_ENABLE() REG_SET(RCC->AHB1LPENR, DMA1_RCC_PATTERN) |
| #define | DMA1_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, DMA1_RCC_PATTERN) |
| #define | DMA2_RCC_PATTERN ( 0x1 << 22u ) |
| #define | DMA2_RESET() REG_TGL(RCC->AHB1RSTR, DMA2_RCC_PATTERN) |
| #define | DMA2_ENABLE() REG_SET(RCC->AHB1ENR, DMA2_RCC_PATTERN) |
| #define | DMA2_DISABLE() REG_CLR(RCC->AHB1ENR, DMA2_RCC_PATTERN) |
| #define | DMA2_LP_ENABLE() REG_SET(RCC->AHB1LPENR, DMA2_RCC_PATTERN) |
| #define | DMA2_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, DMA2_RCC_PATTERN) |
| #define | DMA2D ( (reg_dma2d_t *) 0x4002b000 ) |
| #define | DMA2D_RCC_PATTERN ( 0x1 << 23u ) |
| #define | DMA2D_RESET() REG_TGL(RCC->AHB1RSTR, DMA1_RCC_PATTERN) |
| #define | DMA2D_ENABLE() REG_SET(RCC->AHB1ENR, DMA1_RCC_PATTERN) |
| #define | DMA2D_DISABLE() REG_CLR(RCC->AHB1ENR, DMA1_RCC_PATTERN) |
| #define | DMA2D_LP_ENABLE() REG_SET(RCC->AHB1LPENR, DMA1_RCC_PATTERN) |
| #define | DMA2D_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, DMA1_RCC_PATTERN) |
| #define | NVIC ( (reg_nvic_t *) 0xe000e100 ) |
| #define | EXTI ( (reg_exti_t *) 0x40013c00 ) |
| #define | ADC1 ( (reg_adc_t *) 0x40012000 ) |
| #define | ADC2 ( (reg_adc_t *) 0x40012100 ) |
| #define | ADC3 ( (reg_adc_t *) 0x40012200 ) |
| #define | ADC1_RCC_PATTERN ( 0x1 << 8u ) |
| #define | ADC1_ENABLE() REG_SET(RCC->APB2ENR, ADC1_RCC_PATTERN) |
| #define | ADC1_DISABLE() REG_CLR(RCC->APB2ENR, ADC1_RCC_PATTERN) |
| #define | ADC1_LP_ENABLE() REG_SET(RCC->APB2LPENR, ADC1_RCC_PATTERN) |
| #define | ADC1_LP_DISABLE() REG_CLR(RCC->APB2LPENR, ADC1_RCC_PATTERN) |
| #define | ADC2_RCC_PATTERN ( 0x1 << 9u ) |
| #define | ADC2_ENABLE() REG_SET(RCC->APB2ENR, ADC2_RCC_PATTERN) |
| #define | ADC2_DISABLE() REG_CLR(RCC->APB2ENR, ADC2_RCC_PATTERN) |
| #define | ADC2_LP_ENABLE() REG_SET(RCC->APB2LPENR, ADC2_RCC_PATTERN) |
| #define | ADC2_LP_DISABLE() REG_CLR(RCC->APB2LPENR, ADC2_RCC_PATTERN) |
| #define | ADC3_RCC_PATTERN ( 0x1 << 10u ) |
| #define | ADC3_ENABLE() REG_SET(RCC->APB2ENR, ADC3_RCC_PATTERN) |
| #define | ADC3_DISABLE() REG_CLR(RCC->APB2ENR, ADC3_RCC_PATTERN) |
| #define | ADC3_LP_ENABLE() REG_SET(RCC->APB2LPENR, ADC3_RCC_PATTERN) |
| #define | ADC3_LP_DISABLE() REG_CLR(RCC->APB2LPENR, ADC3_RCC_PATTERN) |
| #define | ADCx_RESET() REG_TGL(RCC->APB2RSTR, ADC1_RCC_PATTERN) |
| #define | ADCCOM ( (reg_adccom_t *) 0x40012300 ) |
| #define | DAC ( (reg_dac_t *) 0x40007400 ) |
| #define | DAC_RCC_PATTERN ( 0x1 << 29u ) |
| #define | DAC_RESET() REG_TGL(RCC->APB1RSTR, DAC_RCC_PATTERN) |
| #define | DAC_ENABLE() REG_SET(RCC->APB1ENR, DAC_RCC_PATTERN) |
| #define | DAC_DISABLE() REG_CLR(RCC->APB1ENR, DAC_RCC_PATTERN) |
| #define | DAC_LP_ENABLE() REG_SET(RCC->APB1LPENR, DAC_RCC_PATTERN) |
| #define | DAC_LP_DISABLE() REG_CLR(RCC->APB1LPENR, DAC_RCC_PATTERN) |
| #define | DCMI ( (reg_dcmi_t *) 0x50050000 ) |
| #define | DCMI_RCC_PATTERN ( 0x1 << 0u ) |
| #define | DCMI_RESET() REG_TGL(RCC->AHB2RSTR, DCMI_RCC_PATTERN) |
| #define | DCMI_ENABLE() REG_SET(RCC->AHB2ENR, DCMI_RCC_PATTERN) |
| #define | DCMI_DISABLE() REG_CLR(RCC->AHB2ENR, DCMI_RCC_PATTERN) |
| #define | DCMI_LP_ENABLE() REG_SET(RCC->AHB2LPENR, DCMI_RCC_PATTERN) |
| #define | DCMI_LP_DISABLE() REG_CLR(RCC->AHB2LPENR, DCMI_RCC_PATTERN) |
| #define | LTDC ( (reg_ltdc_t *) 0x40016800 ) |
| #define | LTDC_RCC_PATTERN ( 0x1 << 26u ) |
| #define | LTDC_RESET() REG_TGL(RCC->APB2RSTR, LTDC_RCC_PATTERN) |
| #define | LTDC_ENABLE() REG_SET(RCC->APB2ENR, LTDC_RCC_PATTERN) |
| #define | LTDC_DISABLE() REG_CLR(RCC->APB2ENR, LTDC_RCC_PATTERN) |
| #define | LTDC_LP_ENABLE() REG_SET(RCC->APB2LPENR, LTDC_RCC_PATTERN) |
| #define | LTDC_LP_DISABLE() REG_CLR(RCC->APB2LPENR, LTDC_RCC_PATTERN) |
| #define | TIM1 ( (reg_tim_t *) 0x40010000 ) |
| #define | TIM2 ( (reg_tim_t *) 0x40000000 ) |
| #define | TIM3 ( (reg_tim_t *) 0x40000400 ) |
| #define | TIM4 ( (reg_tim_t *) 0x40000800 ) |
| #define | TIM5 ( (reg_tim_t *) 0x40000c00 ) |
| #define | TIM6 ( (reg_tim_t *) 0x40001000 ) |
| #define | TIM7 ( (reg_tim_t *) 0x40001400 ) |
| #define | TIM8 ( (reg_tim_t *) 0x40010400 ) |
| #define | TIM9 ( (reg_tim_t *) 0x40014000 ) |
| #define | TIM10 ( (reg_tim_t *) 0x40014400 ) |
| #define | TIM11 ( (reg_tim_t *) 0x40014800 ) |
| #define | TIM12 ( (reg_tim_t *) 0x40001800 ) |
| #define | TIM13 ( (reg_tim_t *) 0x40001c00 ) |
| #define | TIM14 ( (reg_tim_t *) 0x40002000 ) |
| #define | TIM1_RCC_PATTERN ( 0x1 << 0u ) |
| #define | TIM1_RESET() REG_TGL(RCC->APB2RSTR, TIM1_RCC_PATTERN) |
| #define | TIM1_ENABLE() REG_SET(RCC->APB2ENR, TIM1_RCC_PATTERN) |
| #define | TIM1_DISABLE() REG_CLR(RCC->APB2ENR, TIM1_RCC_PATTERN) |
| #define | TIM1_LP_ENABLE() REG_SET(RCC->APB2LPENR, TIM1_RCC_PATTERN) |
| #define | TIM1_LP_DISABLE() REG_CLR(RCC->APB2LPENR, TIM1_RCC_PATTERN) |
| #define | TIM2_RCC_PATTERN ( 0x1 << 0u ) |
| #define | TIM2_RESET() REG_TGL(RCC->APB1RSTR, TIM2_RCC_PATTERN) |
| #define | TIM2_ENABLE() REG_SET(RCC->APB1ENR, TIM2_RCC_PATTERN) |
| #define | TIM2_DISABLE() REG_CLR(RCC->APB1ENR, TIM2_RCC_PATTERN) |
| #define | TIM2_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM2_RCC_PATTERN) |
| #define | TIM2_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM2_RCC_PATTERN) |
| #define | TIM3_RCC_PATTERN ( 0x1 << 1u ) |
| #define | TIM3_RESET() REG_TGL(RCC->APB1RSTR, TIM3_RCC_PATTERN) |
| #define | TIM3_ENABLE() REG_SET(RCC->APB1ENR, TIM3_RCC_PATTERN) |
| #define | TIM3_DISABLE() REG_CLR(RCC->APB1ENR, TIM3_RCC_PATTERN) |
| #define | TIM3_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM3_RCC_PATTERN) |
| #define | TIM3_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM3_RCC_PATTERN) |
| #define | TIM4_RCC_PATTERN ( 0x1 << 2u ) |
| #define | TIM4_RESET() REG_TGL(RCC->APB1RSTR, TIM4_RCC_PATTERN) |
| #define | TIM4_ENABLE() REG_SET(RCC->APB1ENR, TIM4_RCC_PATTERN) |
| #define | TIM4_DISABLE() REG_CLR(RCC->APB1ENR, TIM4_RCC_PATTERN) |
| #define | TIM4_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM4_RCC_PATTERN) |
| #define | TIM4_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM4_RCC_PATTERN) |
| #define | TIM5_RCC_PATTERN ( 0x1 << 3u ) |
| #define | TIM5_RESET() REG_TGL(RCC->APB1RSTR, TIM5_RCC_PATTERN) |
| #define | TIM5_ENABLE() REG_SET(RCC->APB1ENR, TIM5_RCC_PATTERN) |
| #define | TIM5_DISABLE() REG_CLR(RCC->APB1ENR, TIM5_RCC_PATTERN) |
| #define | TIM5_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM5_RCC_PATTERN) |
| #define | TIM5_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM5_RCC_PATTERN) |
| #define | TIM6_RCC_PATTERN ( 0x1 << 4u ) |
| #define | TIM6_RESET() REG_TGL(RCC->APB1RSTR, TIM6_RCC_PATTERN) |
| #define | TIM6_ENABLE() REG_SET(RCC->APB1ENR, TIM6_RCC_PATTERN) |
| #define | TIM6_DISABLE() REG_CLR(RCC->APB1ENR, TIM6_RCC_PATTERN) |
| #define | TIM6_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM6_RCC_PATTERN) |
| #define | TIM6_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM6_RCC_PATTERN) |
| #define | TIM7_RCC_PATTERN ( 0x1 << 5u ) |
| #define | TIM7_RESET() REG_TGL(RCC->APB1RSTR, TIM7_RCC_PATTERN) |
| #define | TIM7_ENABLE() REG_SET(RCC->APB1ENR, TIM7_RCC_PATTERN) |
| #define | TIM7_DISABLE() REG_CLR(RCC->APB1ENR, TIM7_RCC_PATTERN) |
| #define | TIM7_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM7_RCC_PATTERN) |
| #define | TIM7_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM7_RCC_PATTERN) |
| #define | TIM8_RCC_PATTERN ( 0x1 << 1u ) |
| #define | TIM8_RESET() REG_TGL(RCC->APB2RSTR, TIM8_RCC_PATTERN) |
| #define | TIM8_ENABLE() REG_SET(RCC->APB2ENR, TIM8_RCC_PATTERN) |
| #define | TIM8_DISABLE() REG_CLR(RCC->APB2ENR, TIM8_RCC_PATTERN) |
| #define | TIM8_LP_ENABLE() REG_SET(RCC->APB2LPENR, TIM8_RCC_PATTERN) |
| #define | TIM8_LP_DISABLE() REG_CLR(RCC->APB2LPENR, TIM8_RCC_PATTERN) |
| #define | TIM9_RCC_PATTERN ( 0x1 << 16u ) |
| #define | TIM9_RESET() REG_TGL(RCC->APB2RSTR, TIM9_RCC_PATTERN) |
| #define | TIM9_ENABLE() REG_SET(RCC->APB2ENR, TIM9_RCC_PATTERN) |
| #define | TIM9_DISABLE() REG_CLR(RCC->APB2ENR, TIM9_RCC_PATTERN) |
| #define | TIM9_LP_ENABLE() REG_SET(RCC->APB2LPENR, TIM9_RCC_PATTERN) |
| #define | TIM9_LP_DISABLE() REG_CLR(RCC->APB2LPENR, TIM9_RCC_PATTERN) |
| #define | TIM10_RCC_PATTERN ( 0x1 << 17u ) |
| #define | TIM10_RESET() REG_TGL(RCC->APB2RSTR, TIM10_RCC_PATTERN) |
| #define | TIM10_ENABLE() REG_SET(RCC->APB2ENR, TIM10_RCC_PATTERN) |
| #define | TIM10_DISABLE() REG_CLR(RCC->APB2ENR, TIM10_RCC_PATTERN) |
| #define | TIM10_LP_ENABLE() REG_SET(RCC->APB2LPENR, TIM10_RCC_PATTERN) |
| #define | TIM10_LP_DISABLE() REG_CLR(RCC->APB2LPENR, TIM10_RCC_PATTERN) |
| #define | TIM11_RCC_PATTERN ( 0x1 << 18u ) |
| #define | TIM11_RESET() REG_TGL(RCC->APB2RSTR, TIM11_RCC_PATTERN) |
| #define | TIM11_ENABLE() REG_SET(RCC->APB2ENR, TIM11_RCC_PATTERN) |
| #define | TIM11_DISABLE() REG_CLR(RCC->APB2ENR, TIM11_RCC_PATTERN) |
| #define | TIM11_LP_ENABLE() REG_SET(RCC->APB2LPENR, TIM11_RCC_PATTERN) |
| #define | TIM11_LP_DISABLE() REG_CLR(RCC->APB2LPENR, TIM11_RCC_PATTERN) |
| #define | TIM12_RCC_PATTERN ( 0x1 << 6u ) |
| #define | TIM12_RESET() REG_TGL(RCC->APB1RSTR, TIM12_RCC_PATTERN) |
| #define | TIM12_ENABLE() REG_SET(RCC->APB1ENR, TIM12_RCC_PATTERN) |
| #define | TIM12_DISABLE() REG_CLR(RCC->APB1ENR, TIM12_RCC_PATTERN) |
| #define | TIM12_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM12_RCC_PATTERN) |
| #define | TIM12_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM12_RCC_PATTERN) |
| #define | TIM13_RCC_PATTERN ( 0x1 << 7u ) |
| #define | TIM13_RESET() REG_TGL(RCC->APB1RSTR, TIM13_RCC_PATTERN) |
| #define | TIM13_ENABLE() REG_SET(RCC->APB1ENR, TIM13_RCC_PATTERN) |
| #define | TIM13_DISABLE() REG_CLR(RCC->APB1ENR, TIM13_RCC_PATTERN) |
| #define | TIM13_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM13_RCC_PATTERN) |
| #define | TIM13_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM13_RCC_PATTERN) |
| #define | TIM14_RCC_PATTERN ( 0x1 << 8u ) |
| #define | TIM14_RESET() REG_TGL(RCC->APB1RSTR, TIM14_RCC_PATTERN) |
| #define | TIM14_ENABLE() REG_SET(RCC->APB1ENR, TIM14_RCC_PATTERN) |
| #define | TIM14_DISABLE() REG_CLR(RCC->APB1ENR, TIM14_RCC_PATTERN) |
| #define | TIM14_LP_ENABLE() REG_SET(RCC->APB1LPENR, TIM14_RCC_PATTERN) |
| #define | TIM14_LP_DISABLE() REG_CLR(RCC->APB1LPENR, TIM14_RCC_PATTERN) |
| #define | IWDG ( (reg_iwdg_t *) 0x40003000 ) |
| #define | WWDG ( (reg_wwdg_t *) 0x40002c00 ) |
| #define | WWDG_RCC_PATTERN ( 0x1 << 11u ) |
| #define | WWDG_RESET() REG_TGL(RCC->APB1RSTR, WWDG_RCC_PATTERN) |
| #define | WWDG_ENABLE() REG_SET(RCC->APB1ENR, WWDG_RCC_PATTERN) |
| #define | WWDG_DISABLE() REG_CLR(RCC->APB1ENR, WWDG_RCC_PATTERN) |
| #define | WWDG_LP_ENABLE() REG_SET(RCC->APB1LPENR, WWDG_RCC_PATTERN) |
| #define | WWDG_LP_DISABLE() REG_CLR(RCC->APB1LPENR, WWDG_RCC_PATTERN) |
| #define | CRYP ( (reg_cryp_t *) 0x50060000 ) |
| #define | CRYP_RCC_PATTERN ( 0x1 << 4u ) |
| #define | CRYP_RESET() REG_TGL(RCC->AHB2RSTR, CRYP_RCC_PATTERN) |
| #define | CRYP_ENABLE() REG_SET(RCC->AHB2ENR, CRYP_RCC_PATTERN) |
| #define | CRYP_DISABLE() REG_CLR(RCC->AHB2ENR, CRYP_RCC_PATTERN) |
| #define | CRYP_LP_ENABLE() REG_SET(RCC->AHB2LPENR, CRYP_RCC_PATTERN) |
| #define | CRYP_LP_DISABLE() REG_CLR(RCC->AHB2LPENR, CRYP_RCC_PATTERN) |
| #define | RNG ( (reg_rng_t *) 0x50060800 ) |
| #define | RNG_RCC_PATTERN ( 0x1 << 6u ) |
| #define | RNG_RESET() REG_TGL(RCC->AHB2RSTR, RNG_RCC_PATTERN) |
| #define | RNG_ENABLE() REG_SET(RCC->AHB2ENR, RNG_RCC_PATTERN) |
| #define | RNG_DISABLE() REG_CLR(RCC->AHB2ENR, RNG_RCC_PATTERN) |
| #define | RNG_LP_ENABLE() REG_SET(RCC->AHB2LPENR, RNG_RCC_PATTERN) |
| #define | RNG_LP_DISABLE() REG_CLR(RCC->AHB2LPENR, RNG_RCC_PATTERN) |
| #define | HASH ( (reg_hash_t *) 0x50060400 ) |
| #define | HASH_RCC_PATTERN ( 0x1 << 5u ) |
| #define | HASH_RESET() REG_TGL(RCC->AHB2RSTR, HASH_RCC_PATTERN) |
| #define | HASH_ENABLE() REG_SET(RCC->AHB2ENR, HASH_RCC_PATTERN) |
| #define | HASH_DISABLE() REG_CLR(RCC->AHB2ENR, HASH_RCC_PATTERN) |
| #define | HASH_LP_ENABLE() REG_SET(RCC->AHB2LPENR, HASH_RCC_PATTERN) |
| #define | HASH_LP_DISABLE() REG_CLR(RCC->AHB2LPENR, HASH_RCC_PATTERN) |
| #define | RTC ( (reg_rtc_t *) 0x40002800 ) |
| #define | I2C1 ( (reg_i2c_t *) 0x40005400 ) |
| #define | I2C2 ( (reg_i2c_t *) 0x40005800 ) |
| #define | I2C3 ( (reg_i2c_t *) 0x40005c00 ) |
| #define | I2C1_RCC_PATTERN ( 0x1 << 21u ) |
| #define | I2C1_RESET() REG_TGL(RCC->APB1RSTR, I2C1_RCC_PATTERN) |
| #define | I2C1_ENABLE() REG_SET(RCC->APB1ENR, I2C1_RCC_PATTERN) |
| #define | I2C1_DISABLE() REG_CLR(RCC->APB1ENR, I2C1_RCC_PATTERN) |
| #define | I2C1_LP_ENABLE() REG_SET(RCC->APB1LPENR, I2C1_RCC_PATTERN) |
| #define | I2C1_LP_DISABLE() REG_CLR(RCC->APB1LPENR, I2C1_RCC_PATTERN) |
| #define | I2C2_RCC_PATTERN ( 0x1 << 22u ) |
| #define | I2C2_RESET() REG_TGL(RCC->APB1RSTR, I2C2_RCC_PATTERN) |
| #define | I2C2_ENABLE() REG_SET(RCC->APB1ENR, I2C2_RCC_PATTERN) |
| #define | I2C2_DISABLE() REG_CLR(RCC->APB1ENR, I2C2_RCC_PATTERN) |
| #define | I2C2_LP_ENABLE() REG_SET(RCC->APB1LPENR, I2C2_RCC_PATTERN) |
| #define | I2C2_LP_DISABLE() REG_CLR(RCC->APB1LPENR, I2C2_RCC_PATTERN) |
| #define | I2C3_RCC_PATTERN ( 0x1 << 23u ) |
| #define | I2C3_RESET() REG_TGL(RCC->APB1RSTR, I2C3_RCC_PATTERN) |
| #define | I2C3_ENABLE() REG_SET(RCC->APB1ENR, I2C3_RCC_PATTERN) |
| #define | I2C3_DISABLE() REG_CLR(RCC->APB1ENR, I2C3_RCC_PATTERN) |
| #define | I2C3_LP_ENABLE() REG_SET(RCC->APB1LPENR, I2C3_RCC_PATTERN) |
| #define | I2C3_LP_DISABLE() REG_CLR(RCC->APB1LPENR, I2C3_RCC_PATTERN) |
| #define | SPI1 ( (reg_spi_t *) 0x40013000 ) |
| #define | SPI2 ( (reg_spi_t *) 0x40003800 ) |
| #define | SPI3 ( (reg_spi_t *) 0x40003c00 ) |
| #define | SPI4 ( (reg_spi_t *) 0x40013400 ) |
| #define | SPI5 ( (reg_spi_t *) 0x40015000 ) |
| #define | SPI6 ( (reg_spi_t *) 0x40015400 ) |
| #define | SPI1_RCC_PATTERN ( 0x1 << 12u ) |
| #define | SPI1_RESET() REG_TGL(RCC->APB2RSTR, SPI1_RCC_PATTERN) |
| #define | SPI1_ENABLE() REG_SET(RCC->APB2ENR, SPI1_RCC_PATTERN) |
| #define | SPI1_DISABLE() REG_CLR(RCC->APB2ENR, SPI1_RCC_PATTERN) |
| #define | SPI1_LP_ENABLE() REG_SET(RCC->APB2LPENR, SPI1_RCC_PATTERN) |
| #define | SPI1_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SPI1_RCC_PATTERN) |
| #define | SPI2_RCC_PATTERN ( 0x1 << 14u ) |
| #define | SPI2_RESET() REG_TGL(RCC->APB1RSTR, SPI2_RCC_PATTERN) |
| #define | SPI2_ENABLE() REG_SET(RCC->APB1ENR, SPI2_RCC_PATTERN) |
| #define | SPI2_DISABLE() REG_CLR(RCC->APB1ENR, SPI2_RCC_PATTERN) |
| #define | SPI2_LP_ENABLE() REG_SET(RCC->APB1LPENR, SPI2_RCC_PATTERN) |
| #define | SPI2_LP_DISABLE() REG_CLR(RCC->APB1LPENR, SPI2_RCC_PATTERN) |
| #define | SPI3_RCC_PATTERN ( 0x1 << 15u ) |
| #define | SPI3_RESET() REG_TGL(RCC->APB1RSTR, SPI3_RCC_PATTERN) |
| #define | SPI3_ENABLE() REG_SET(RCC->APB1ENR, SPI3_RCC_PATTERN) |
| #define | SPI3_DISABLE() REG_CLR(RCC->APB1ENR, SPI3_RCC_PATTERN) |
| #define | SPI3_LP_ENABLE() REG_SET(RCC->APB1LPENR, SPI3_RCC_PATTERN) |
| #define | SPI3_LP_DISABLE() REG_CLR(RCC->APB1LPENR, SPI3_RCC_PATTERN) |
| #define | SPI4_RCC_PATTERN ( 0x1 << 13u ) |
| #define | SPI4_RESET() REG_TGL(RCC->APB2RSTR, SPI4_RCC_PATTERN) |
| #define | SPI4_ENABLE() REG_SET(RCC->APB2ENR, SPI4_RCC_PATTERN) |
| #define | SPI4_DISABLE() REG_CLR(RCC->APB2ENR, SPI4_RCC_PATTERN) |
| #define | SPI4_LP_ENABLE() REG_SET(RCC->APB2LPENR, SPI4_RCC_PATTERN) |
| #define | SPI4_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SPI4_RCC_PATTERN) |
| #define | SPI5_RCC_PATTERN ( 0x1 << 20u ) |
| #define | SPI5_RESET() REG_TGL(RCC->APB2RSTR, SPI5_RCC_PATTERN) |
| #define | SPI5_ENABLE() REG_SET(RCC->APB2ENR, SPI5_RCC_PATTERN) |
| #define | SPI5_DISABLE() REG_CLR(RCC->APB2ENR, SPI5_RCC_PATTERN) |
| #define | SPI5_LP_ENABLE() REG_SET(RCC->APB2LPENR, SPI5_RCC_PATTERN) |
| #define | SPI5_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SPI5_RCC_PATTERN) |
| #define | SPI6_RCC_PATTERN ( 0x1 << 21u ) |
| #define | SPI6_RESET() REG_TGL(RCC->APB2RSTR, SPI6_RCC_PATTERN) |
| #define | SPI6_ENABLE() REG_SET(RCC->APB2ENR, SPI6_RCC_PATTERN) |
| #define | SPI6_DISABLE() REG_CLR(RCC->APB2ENR, SPI6_RCC_PATTERN) |
| #define | SPI6_LP_ENABLE() REG_SET(RCC->APB2LPENR, SPI6_RCC_PATTERN) |
| #define | SPI6_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SPI6_RCC_PATTERN) |
| #define | SAI1 ( (reg_sai_t *) 0x40015800 ) |
| #define | SAI1_RCC_PATTERN ( 0x1 << 22u ) |
| #define | SAI1_RESET() REG_TGL(RCC->APB2RSTR, SAI1_RCC_PATTERN) |
| #define | SAI1_ENABLE() REG_SET(RCC->APB2ENR, SAI1_RCC_PATTERN) |
| #define | SAI1_DISABLE() REG_CLR(RCC->APB2ENR, SAI1_RCC_PATTERN) |
| #define | SAI1_LP_ENABLE() REG_SET(RCC->APB2LPENR, SAI1_RCC_PATTERN) |
| #define | SAI1_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SAI1_RCC_PATTERN) |
| #define | USART1 ( (reg_usart_t *) 0x40011000 ) |
| #define | USART2 ( (reg_usart_t *) 0x40004400 ) |
| #define | USART3 ( (reg_usart_t *) 0x40004800 ) |
| #define | UART4 ( (reg_usart_t *) 0x40004c00 ) |
| #define | UART5 ( (reg_usart_t *) 0x40005000 ) |
| #define | USART6 ( (reg_usart_t *) 0x40011400 ) |
| #define | USART7 ( (reg_usart_t *) 0x40007800 ) |
| #define | USART8 ( (reg_usart_t *) 0x40007c00 ) |
| #define | USART1_RCC_PATTERN ( 0x1 << 4u ) |
| #define | USART1_RESET() REG_TGL(RCC->APB2RSTR, USART1_RCC_PATTERN) |
| #define | USART1_ENABLE() REG_SET(RCC->APB2ENR, USART1_RCC_PATTERN) |
| #define | USART1_DISABLE() REG_CLR(RCC->APB2ENR, USART1_RCC_PATTERN) |
| #define | USART1_LP_ENABLE() REG_SET(RCC->APB2LPENR, USART1_RCC_PATTERN) |
| #define | USART1_LP_DISABLE() REG_CLR(RCC->APB2LPENR, USART1_RCC_PATTERN) |
| #define | USART2_RCC_PATTERN ( 0x1 << 17u ) |
| #define | USART2_RESET() REG_TGL(RCC->APB1RSTR, USART2_RCC_PATTERN) |
| #define | USART2_ENABLE() REG_SET(RCC->APB1ENR, USART2_RCC_PATTERN) |
| #define | USART2_DISABLE() REG_CLR(RCC->APB1ENR, USART2_RCC_PATTERN) |
| #define | USART2_LP_ENABLE() REG_SET(RCC->APB1LPENR, USART2_RCC_PATTERN) |
| #define | USART2_LP_DISABLE() REG_CLR(RCC->APB1LPENR, USART2_RCC_PATTERN) |
| #define | USART3_RCC_PATTERN ( 0x1 << 18u ) |
| #define | USART3_RESET() REG_TGL(RCC->APB1RSTR, USART3_RCC_PATTERN) |
| #define | USART3_ENABLE() REG_SET(RCC->APB1ENR, USART3_RCC_PATTERN) |
| #define | USART3_DISABLE() REG_CLR(RCC->APB1ENR, USART3_RCC_PATTERN) |
| #define | USART3_LP_ENABLE() REG_SET(RCC->APB1LPENR, USART3_RCC_PATTERN) |
| #define | USART3_LP_DISABLE() REG_CLR(RCC->APB1LPENR, USART3_RCC_PATTERN) |
| #define | UART4_RCC_PATTERN ( 0x1 << 19u ) |
| #define | UART4_RESET() REG_TGL(RCC->APB1RSTR, UART4_RCC_PATTERN) |
| #define | UART4_ENABLE() REG_SET(RCC->APB1ENR, UART4_RCC_PATTERN) |
| #define | UART4_DISABLE() REG_CLR(RCC->APB1ENR, UART4_RCC_PATTERN) |
| #define | UART4_LP_ENABLE() REG_SET(RCC->APB1LPENR, UART4_RCC_PATTERN) |
| #define | UART4_LP_DISABLE() REG_CLR(RCC->APB1LPENR, UART4_RCC_PATTERN) |
| #define | UART5_RCC_PATTERN ( 0x1 << 20u ) |
| #define | UART5_RESET() REG_TGL(RCC->APB1RSTR, UART5_RCC_PATTERN) |
| #define | UART5_ENABLE() REG_SET(RCC->APB1ENR, UART5_RCC_PATTERN) |
| #define | UART5_DISABLE() REG_CLR(RCC->APB1ENR, UART5_RCC_PATTERN) |
| #define | UART5_LP_ENABLE() REG_SET(RCC->APB1LPENR, UART5_RCC_PATTERN) |
| #define | UART5_LP_DISABLE() REG_CLR(RCC->APB1LPENR, UART5_RCC_PATTERN) |
| #define | USART6_RCC_PATTERN ( 0x1 << 5u ) |
| #define | USART6_RESET() REG_TGL(RCC->APB2RSTR, USART6_RCC_PATTERN) |
| #define | USART6_ENABLE() REG_SET(RCC->APB2ENR, USART6_RCC_PATTERN) |
| #define | USART6_DISABLE() REG_CLR(RCC->APB2ENR, USART6_RCC_PATTERN) |
| #define | USART6_LP_ENABLE() REG_SET(RCC->APB2LPENR, USART6_RCC_PATTERN) |
| #define | USART6_LP_DISABLE() REG_CLR(RCC->APB2LPENR, USART6_RCC_PATTERN) |
| #define | USART7_RCC_PATTERN ( 0x1 << 30u ) |
| #define | USART7_RESET() REG_TGL(RCC->APB1RSTR, USART7_RCC_PATTERN) |
| #define | USART7_ENABLE() REG_SET(RCC->APB1ENR, USART7_RCC_PATTERN) |
| #define | USART7_DISABLE() REG_CLR(RCC->APB1ENR, USART7_RCC_PATTERN) |
| #define | USART7_LP_ENABLE() REG_SET(RCC->APB1LPENR, USART7_RCC_PATTERN) |
| #define | USART7_LP_DISABLE() REG_CLR(RCC->APB1LPENR, USART7_RCC_PATTERN) |
| #define | USART8_RCC_PATTERN ( 0x1 << 31u ) |
| #define | USART8_RESET() REG_TGL(RCC->APB1RSTR, USART8_RCC_PATTERN) |
| #define | USART8_ENABLE() REG_SET(RCC->APB1ENR, USART8_RCC_PATTERN) |
| #define | USART8_DISABLE() REG_CLR(RCC->APB1ENR, USART8_RCC_PATTERN) |
| #define | USART8_LP_ENABLE() REG_SET(RCC->APB1LPENR, USART8_RCC_PATTERN) |
| #define | USART8_LP_DISABLE() REG_CLR(RCC->APB1LPENR, USART8_RCC_PATTERN) |
| #define | SDIO ( (reg_sdio_t *) 0x40006400 ) |
| #define | SDIO_RCC_PATTERN ( 0x1 << 11u ) |
| #define | SDIO_RESET() REG_TGL(RCC->APB2RSTR, SDIO_RCC_PATTERN) |
| #define | SDIO_ENABLE() REG_SET(RCC->APB2ENR, SDIO_RCC_PATTERN) |
| #define | SDIO_DISABLE() REG_CLR(RCC->APB2ENR, SDIO_RCC_PATTERN) |
| #define | SDIO_LP_ENABLE() REG_SET(RCC->APB2LPENR, SDIO_RCC_PATTERN) |
| #define | SDIO_LP_DISABLE() REG_CLR(RCC->APB2LPENR, SDIO_RCC_PATTERN) |
| #define | CAN1 ( (reg_can_t *) 0x40006400 ) |
| #define | CAN2 ( (reg_can_t *) 0x40006800 ) |
| #define | CAN1_RCC_PATTERN ( 0x1 << 25u ) |
| #define | CAN1_RESET() REG_TGL(RCC->APB1RSTR, CAN1_RCC_PATTERN) |
| #define | CAN1_ENABLE() REG_SET(RCC->APB1ENR, CAN1_RCC_PATTERN) |
| #define | CAN1_DISABLE() REG_CLR(RCC->APB1ENR, CAN1_RCC_PATTERN) |
| #define | CAN1_LP_ENABLE() REG_SET(RCC->APB1LPENR, CAN1_RCC_PATTERN) |
| #define | CAN1_LP_DISABLE() REG_CLR(RCC->APB1LPENR, CAN1_RCC_PATTERN) |
| #define | CAN2_RCC_PATTERN ( 0x1 << 26u ) |
| #define | CAN2_RESET() REG_TGL(RCC->APB1RSTR, CAN2_RCC_PATTERN) |
| #define | CAN2_ENABLE() REG_SET(RCC->APB1ENR, CAN2_RCC_PATTERN) |
| #define | CAN2_DISABLE() REG_CLR(RCC->APB1ENR, CAN2_RCC_PATTERN) |
| #define | CAN2_LP_ENABLE() REG_SET(RCC->APB1LPENR, CAN2_RCC_PATTERN) |
| #define | CAN2_LP_DISABLE() REG_CLR(RCC->APB1LPENR, CAN2_RCC_PATTERN) |
| #define | FMC ( (reg_fmc_t *) 0xa0000000 ) |
| #define | FMC_RCC_PATTERN ( 0x1 << 0u ) |
| #define | FMC_RESET() REG_TGL(RCC->AHB3RSTR, FMC_RCC_PATTERN) |
| #define | FMC_ENABLE() REG_SET(RCC->AHB3ENR, FMC_RCC_PATTERN) |
| #define | FMC_DISABLE() REG_CLR(RCC->AHB3ENR, FMC_RCC_PATTERN) |
| #define | FMC_LP_ENABLE() REG_SET(RCC->AHB3LPENR, FMC_RCC_PATTERN) |
| #define | FMC_LP_DISABLE() REG_CLR(RCC->AHB3LPENR, FMC_RCC_PATTERN) |
| #define | MPU ( (reg_mpu_t *) 0xe000ed90 ) |
| #define | SCB ( (reg_scb_t *) 0xe000ed00 ) |
| #define | STK ( (reg_stk_t *) 0xe000e010 ) |
| #define | FPU ( (reg_fpu_t *) 0xe000ed88 ) |
| #define | DBG ( (reg_dbg_t *) 0xe0042000 ) |
| #define | SRAM1_RCC_PATTERN ( 0x1 << 16u ) |
| #define | SRAM1_LP_ENABLE() REG_SET(RCC->AHB1LPENR, SRAM1_RCC_PATTERN) |
| #define | SRAM1_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, SRAM1_RCC_PATTERN) |
| #define | SRAM2_RCC_PATTERN ( 0x1 << 17u ) |
| #define | SRAM2_LP_ENABLE() REG_SET(RCC->AHB1LPENR, SRAM2_RCC_PATTERN) |
| #define | SRAM2_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, SRAM2_RCC_PATTERN) |
| #define | SRAM3_RCC_PATTERN ( 0x1 << 19u ) |
| #define | SRAM3_LP_ENABLE() REG_SET(RCC->AHB1LPENR, SRAM3_RCC_PATTERN) |
| #define | SRAM3_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, SRAM3_RCC_PATTERN) |
| #define | BKPSRAM_RCC_PATTERN ( 0x1 << 18u ) |
| #define | BKPSRAM_ENABLE() REG_SET(RCC->AHB3ENR, BKPSRAM_RCC_PATTERN) |
| #define | BKPSRAM_DISABLE() REG_CLR(RCC->AHB3ENR, BKPSRAM_RCC_PATTERN) |
| #define | BKPSRAM_LP_ENABLE() REG_SET(RCC->AHB1LPENR, BKPSRAM_RCC_PATTERN) |
| #define | BKPSRAM_LP_DISABLE() REG_CLR(RCC->AHB1LPENR, BKPSRAM_RCC_PATTERN) |
| #define | CCM_RCC_PATTERN ( 0x1 << 20u ) |
| #define | CCM_ENABLE() REG_SET(RCC->AHB1ENR, CCM_RCC_PATTERN) |
| #define | CCM_DISABLE() REG_CLR(RCC->AHB1ENR, CCM_RCC_PATTERN) |
Registries for STM32F4xx.
| #define REG_TGL | ( | REG, | |
| BIT | |||
| ) |
1.8.15