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InES Hardware Abstraction Layer
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Representation of RCC register. More...
#include <reg_stm32f4xx.h>
Data Fields | |
| volatile uint32_t | CR |
| volatile uint32_t | PLLCFGR |
| volatile uint32_t | CFGR |
| volatile uint32_t | CIR |
| volatile uint32_t | AHB1RSTR |
| volatile uint32_t | AHB2RSTR |
| volatile uint32_t | AHB3RSTR |
| uint32_t | RESERVED |
| volatile uint32_t | APB1RSTR |
| volatile uint32_t | APB2RSTR |
| uint32_t | RESERVED1 [2] |
| volatile uint32_t | AHB1ENR |
| volatile uint32_t | AHB2ENR |
| volatile uint32_t | AHB3ENR |
| uint32_t | RESERVED2 |
| volatile uint32_t | APB1ENR |
| volatile uint32_t | APB2ENR |
| uint32_t | RESERVED3 [2] |
| volatile uint32_t | AHB1LPENR |
| volatile uint32_t | AHB2LPENR |
| volatile uint32_t | AHB3LPENR |
| uint32_t | RESERVED4 |
| volatile uint32_t | APB1LPENR |
| volatile uint32_t | APB2LPENR |
| uint32_t | RESERVED5 [2] |
| volatile uint32_t | BDCR |
| volatile uint32_t | CSR |
| uint32_t | RESERVED6 [2] |
| volatile uint32_t | SSCGR |
| volatile uint32_t | PLLI2SCFGR |
| volatile uint32_t | PLLSAICFGR |
| volatile uint32_t | DCKCFGR |
Representation of RCC register.
Described in reference manual p.147ff.
| volatile uint32_t reg_rcc_t::AHB1ENR |
AHB1 peripheral clock enable register.
| volatile uint32_t reg_rcc_t::AHB1LPENR |
AHB1 peripheral clock enable in lp register.
| volatile uint32_t reg_rcc_t::AHB1RSTR |
AHB1 peripheral reset register.
| volatile uint32_t reg_rcc_t::AHB2ENR |
AHB2 peripheral clock enable register.
| volatile uint32_t reg_rcc_t::AHB2LPENR |
AHB2 peripheral clock enable in lp register.
| volatile uint32_t reg_rcc_t::AHB2RSTR |
AHB2 peripheral reset register.
| volatile uint32_t reg_rcc_t::AHB3ENR |
AHB3 peripheral clock enable register.
| volatile uint32_t reg_rcc_t::AHB3LPENR |
AHB3 peripheral clock enable in lp register.
| volatile uint32_t reg_rcc_t::AHB3RSTR |
AHB3 peripheral reset register.
| volatile uint32_t reg_rcc_t::APB1ENR |
APB1 peripheral clock enable register.
| volatile uint32_t reg_rcc_t::APB1LPENR |
APB1 peripheral clock enable in lp register.
| volatile uint32_t reg_rcc_t::APB1RSTR |
APB1 peripheral reset register.
| volatile uint32_t reg_rcc_t::APB2ENR |
APB2 peripheral clock enable register.
| volatile uint32_t reg_rcc_t::APB2LPENR |
APB2 peripheral clock enable in lp register.
| volatile uint32_t reg_rcc_t::APB2RSTR |
APB2 peripheral reset register.
| volatile uint32_t reg_rcc_t::BDCR |
Backup domain control register.
| volatile uint32_t reg_rcc_t::CFGR |
Clock configuration register.
| volatile uint32_t reg_rcc_t::CIR |
Clock interrupt register.
| volatile uint32_t reg_rcc_t::CR |
Clock control register.
| volatile uint32_t reg_rcc_t::CSR |
Clock controll and status register.
| volatile uint32_t reg_rcc_t::DCKCFGR |
Dedicated clock conf. register.
| volatile uint32_t reg_rcc_t::PLLCFGR |
PLL configuration register.
| volatile uint32_t reg_rcc_t::PLLI2SCFGR |
PLLI2S configuration register.
| volatile uint32_t reg_rcc_t::PLLSAICFGR |
PLLSAI configuration register.
| volatile uint32_t reg_rcc_t::SSCGR |
Spreadspectrum clock gen. register.
1.8.15