InES Hardware Abstraction Layer
Data Fields
reg_rcc_t Struct Reference

Representation of RCC register. More...

#include <reg_stm32f4xx.h>

Data Fields

volatile uint32_t CR
 
volatile uint32_t PLLCFGR
 
volatile uint32_t CFGR
 
volatile uint32_t CIR
 
volatile uint32_t AHB1RSTR
 
volatile uint32_t AHB2RSTR
 
volatile uint32_t AHB3RSTR
 
uint32_t RESERVED
 
volatile uint32_t APB1RSTR
 
volatile uint32_t APB2RSTR
 
uint32_t RESERVED1 [2]
 
volatile uint32_t AHB1ENR
 
volatile uint32_t AHB2ENR
 
volatile uint32_t AHB3ENR
 
uint32_t RESERVED2
 
volatile uint32_t APB1ENR
 
volatile uint32_t APB2ENR
 
uint32_t RESERVED3 [2]
 
volatile uint32_t AHB1LPENR
 
volatile uint32_t AHB2LPENR
 
volatile uint32_t AHB3LPENR
 
uint32_t RESERVED4
 
volatile uint32_t APB1LPENR
 
volatile uint32_t APB2LPENR
 
uint32_t RESERVED5 [2]
 
volatile uint32_t BDCR
 
volatile uint32_t CSR
 
uint32_t RESERVED6 [2]
 
volatile uint32_t SSCGR
 
volatile uint32_t PLLI2SCFGR
 
volatile uint32_t PLLSAICFGR
 
volatile uint32_t DCKCFGR
 

Detailed Description

Representation of RCC register.

Described in reference manual p.147ff.

Field Documentation

◆ AHB1ENR

volatile uint32_t reg_rcc_t::AHB1ENR

AHB1 peripheral clock enable register.

◆ AHB1LPENR

volatile uint32_t reg_rcc_t::AHB1LPENR

AHB1 peripheral clock enable in lp register.

◆ AHB1RSTR

volatile uint32_t reg_rcc_t::AHB1RSTR

AHB1 peripheral reset register.

◆ AHB2ENR

volatile uint32_t reg_rcc_t::AHB2ENR

AHB2 peripheral clock enable register.

◆ AHB2LPENR

volatile uint32_t reg_rcc_t::AHB2LPENR

AHB2 peripheral clock enable in lp register.

◆ AHB2RSTR

volatile uint32_t reg_rcc_t::AHB2RSTR

AHB2 peripheral reset register.

◆ AHB3ENR

volatile uint32_t reg_rcc_t::AHB3ENR

AHB3 peripheral clock enable register.

◆ AHB3LPENR

volatile uint32_t reg_rcc_t::AHB3LPENR

AHB3 peripheral clock enable in lp register.

◆ AHB3RSTR

volatile uint32_t reg_rcc_t::AHB3RSTR

AHB3 peripheral reset register.

◆ APB1ENR

volatile uint32_t reg_rcc_t::APB1ENR

APB1 peripheral clock enable register.

◆ APB1LPENR

volatile uint32_t reg_rcc_t::APB1LPENR

APB1 peripheral clock enable in lp register.

◆ APB1RSTR

volatile uint32_t reg_rcc_t::APB1RSTR

APB1 peripheral reset register.

◆ APB2ENR

volatile uint32_t reg_rcc_t::APB2ENR

APB2 peripheral clock enable register.

◆ APB2LPENR

volatile uint32_t reg_rcc_t::APB2LPENR

APB2 peripheral clock enable in lp register.

◆ APB2RSTR

volatile uint32_t reg_rcc_t::APB2RSTR

APB2 peripheral reset register.

◆ BDCR

volatile uint32_t reg_rcc_t::BDCR

Backup domain control register.

◆ CFGR

volatile uint32_t reg_rcc_t::CFGR

Clock configuration register.

◆ CIR

volatile uint32_t reg_rcc_t::CIR

Clock interrupt register.

◆ CR

volatile uint32_t reg_rcc_t::CR

Clock control register.

◆ CSR

volatile uint32_t reg_rcc_t::CSR

Clock controll and status register.

◆ DCKCFGR

volatile uint32_t reg_rcc_t::DCKCFGR

Dedicated clock conf. register.

◆ PLLCFGR

volatile uint32_t reg_rcc_t::PLLCFGR

PLL configuration register.

◆ PLLI2SCFGR

volatile uint32_t reg_rcc_t::PLLI2SCFGR

PLLI2S configuration register.

◆ PLLSAICFGR

volatile uint32_t reg_rcc_t::PLLSAICFGR

PLLSAI configuration register.

◆ SSCGR

volatile uint32_t reg_rcc_t::SSCGR

Spreadspectrum clock gen. register.


The documentation for this struct was generated from the following file: