reg_fmc_sram_t Struct Reference

Representation of SRAM register (Bank 1). More...

#include <reg_stm32f4xx.h>

Data Fields
volatile uint32_t	BCR1
volatile uint32_t	BTR1
volatile uint32_t	BCR2
volatile uint32_t	BTR2
volatile uint32_t	BCR3
volatile uint32_t	BTR3
volatile uint32_t	BCR4
volatile uint32_t	BTR4
uint32_t	RESERVED1 [57]
volatile uint32_t	BWTR1
uint32_t	RESERVED2
volatile uint32_t	BWTR2
uint32_t	RESERVED3
volatile uint32_t	BWTR3
uint32_t	RESERVED4
volatile uint32_t	BWTR4

Detailed Description

Representation of SRAM register (Bank 1).

Field Documentation

BCR1

volatile uint32_t reg_fmc_sram_t::BCR1

(Sub)Bank 1 control register.

BCR2

volatile uint32_t reg_fmc_sram_t::BCR2

(Sub)Bank 2 control register.

BCR3

volatile uint32_t reg_fmc_sram_t::BCR3

(Sub)Bank 3 control register.

BCR4

volatile uint32_t reg_fmc_sram_t::BCR4

(Sub)Bank 4 control register.

BTR1

volatile uint32_t reg_fmc_sram_t::BTR1

(Sub)Bank 1 timing registers.

BTR2

volatile uint32_t reg_fmc_sram_t::BTR2

(Sub)Bank 2 timing registers.

BTR3

volatile uint32_t reg_fmc_sram_t::BTR3

(Sub)Bank 3 timing registers.

BTR4

volatile uint32_t reg_fmc_sram_t::BTR4

(Sub)Bank 4 timing registers.

BWTR1

volatile uint32_t reg_fmc_sram_t::BWTR1

(Sub)Bank 1 write timing registers.

BWTR2

volatile uint32_t reg_fmc_sram_t::BWTR2

(Sub)Bank 2 write timing registers.

BWTR3

volatile uint32_t reg_fmc_sram_t::BWTR3

(Sub)Bank 3 write timing registers.

BWTR4

volatile uint32_t reg_fmc_sram_t::BWTR4

(Sub)Bank 4 write timing registers.

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The documentation for this struct was generated from the following file:

• C:/Temp/Git/CT_Board/Software/Keil/uVision_Pack/Content/Device/Include/reg_stm32f4xx.h