InES Hardware Abstraction Layer
Data Fields
reg_dma_stream_t Struct Reference

Representation of DMA stream register. More...

#include <reg_stm32f4xx.h>

Data Fields

volatile uint32_t CR
 
volatile uint32_t NDTR
 
volatile uint32_t PAR
 
volatile uint32_t M0AR
 
volatile uint32_t M1AR
 
volatile uint32_t FCR
 

Detailed Description

Representation of DMA stream register.

Field Documentation

◆ CR

volatile uint32_t reg_dma_stream_t::CR

Stream configuration register.

◆ FCR

volatile uint32_t reg_dma_stream_t::FCR

FIFO control register.

◆ M0AR

volatile uint32_t reg_dma_stream_t::M0AR

Memory 0 address register.

◆ M1AR

volatile uint32_t reg_dma_stream_t::M1AR

Memory 1 address register.

◆ NDTR

volatile uint32_t reg_dma_stream_t::NDTR

Number of data register.

◆ PAR

volatile uint32_t reg_dma_stream_t::PAR

Peripheral address register.


The documentation for this struct was generated from the following file: