InES Hardware Abstraction Layer
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Representation of DMA stream register. More...
#include <reg_stm32f4xx.h>
Data Fields | |
volatile uint32_t | CR |
volatile uint32_t | NDTR |
volatile uint32_t | PAR |
volatile uint32_t | M0AR |
volatile uint32_t | M1AR |
volatile uint32_t | FCR |
Representation of DMA stream register.
volatile uint32_t reg_dma_stream_t::CR |
Stream configuration register.
volatile uint32_t reg_dma_stream_t::FCR |
FIFO control register.
volatile uint32_t reg_dma_stream_t::M0AR |
Memory 0 address register.
volatile uint32_t reg_dma_stream_t::M1AR |
Memory 1 address register.
volatile uint32_t reg_dma_stream_t::NDTR |
Number of data register.
volatile uint32_t reg_dma_stream_t::PAR |
Peripheral address register.