Representation of CAN register. More...

#include <reg_stm32f4xx.h>

Data Fields
volatile uint32_t	MCR

volatile uint32_t	MSR

volatile uint32_t	TSR

volatile uint32_t	RF0R

volatile uint32_t	RF1R

volatile uint32_t	IER

volatile uint32_t	ESR

volatile uint32_t	BTR

uint32_t	RESERVED1 [88]

volatile uint32_t	TI0R

volatile uint32_t	TDT0R

volatile uint32_t	TDL0R

volatile uint32_t	TDH0R

volatile uint32_t	TI1R

volatile uint32_t	TDT1R

volatile uint32_t	TDL1R

volatile uint32_t	TDH1R

volatile uint32_t	TI2R

volatile uint32_t	TDT2R

volatile uint32_t	TDL2R

volatile uint32_t	TDH2R

volatile uint32_t	RI0R

volatile uint32_t	RDT0R

volatile uint32_t	RDL0R

volatile uint32_t	RDH0R

volatile uint32_t	RI1R

volatile uint32_t	RDT1R

volatile uint32_t	RDL1R

volatile uint32_t	RDH1R

uint32_t	RESERVED2 [12]

volatile uint32_t	FMR

volatile uint32_t	FM1R

uint32_t	RESERVED3

volatile uint32_t	FS1R

uint32_t	RESERVED4

volatile uint32_t	FFA1R

uint32_t	RESERVED5

volatile uint32_t	FA1R

uint32_t	RESERVED6 [8]

volatile uint32_t	FR [28][2]

Detailed Description

Representation of CAN register.

Described in reference manual p.1059ff.

Field Documentation

◆ BTR

volatile uint32_t reg_can_t::BTR

Error status register.

◆ ESR

volatile uint32_t reg_can_t::ESR

Interrupt enable register.

◆ FM1R

volatile uint32_t reg_can_t::FM1R

Filter master register.

◆ IER

volatile uint32_t reg_can_t::IER

Receive FIFO1 register.

◆ MSR

volatile uint32_t reg_can_t::MSR

Master control register.

◆ RDH0R

volatile uint32_t reg_can_t::RDH0R

RX mailbox data low register 0.

◆ RDH1R

volatile uint32_t reg_can_t::RDH1R

RX mailbox data low register 1.

◆ RDL0R

volatile uint32_t reg_can_t::RDL0R

RX mailbox data length and time stamp register 0.

◆ RDL1R

volatile uint32_t reg_can_t::RDL1R

RX mailbox data length and time stamp register 1.

◆ RDT0R

volatile uint32_t reg_can_t::RDT0R

RX mailbox identifier register 0.

◆ RDT1R

volatile uint32_t reg_can_t::RDT1R

RX mailbox identifier register 1.

◆ RESERVED1

uint32_t reg_can_t::RESERVED1[88]

Bit timing register.

◆ RESERVED2

uint32_t reg_can_t::RESERVED2[12]

RX mailbox data high register 1.

◆ RESERVED3

uint32_t reg_can_t::RESERVED3

Filter mode register.

◆ RESERVED4

uint32_t reg_can_t::RESERVED4

Filter scale register.

◆ RESERVED5

uint32_t reg_can_t::RESERVED5

Filter FIFO assignment register.

◆ RESERVED6

uint32_t reg_can_t::RESERVED6[8]

Filter activation register.

◆ RF0R

volatile uint32_t reg_can_t::RF0R

Transmit status register.

◆ RF1R

volatile uint32_t reg_can_t::RF1R

Receive FIFO0 register.

◆ RI0R

volatile uint32_t reg_can_t::RI0R

TX mailbox data high register 2.

◆ RI1R

volatile uint32_t reg_can_t::RI1R

RX mailbox data high register 0.

◆ TDH0R

volatile uint32_t reg_can_t::TDH0R

TX mailbox data low register 0.

◆ TDH1R

volatile uint32_t reg_can_t::TDH1R

TX mailbox data low register 1.

◆ TDH2R

volatile uint32_t reg_can_t::TDH2R

TX mailbox data low register 2.

◆ TDL0R

volatile uint32_t reg_can_t::TDL0R

TX mailbox data length and time stamp register 0.

◆ TDL1R

volatile uint32_t reg_can_t::TDL1R

TX mailbox data length and time stamp register 1.

◆ TDL2R

volatile uint32_t reg_can_t::TDL2R

TX mailbox data length and time stamp register 2.

◆ TDT0R

volatile uint32_t reg_can_t::TDT0R

TX mailbox identifier register 0.

◆ TDT1R

volatile uint32_t reg_can_t::TDT1R

TX mailbox identifier register 1.

◆ TDT2R

volatile uint32_t reg_can_t::TDT2R

TX mailbox identifier register 2.

◆ TI1R

volatile uint32_t reg_can_t::TI1R

TX mailbox data high register 0.

◆ TI2R

volatile uint32_t reg_can_t::TI2R

TX mailbox data high register 1.

◆ TSR

volatile uint32_t reg_can_t::TSR

Master status regiser.

The documentation for this struct was generated from the following file:

C:/Temp/Git/CT_Board/Software/Keil/uVision_Pack/Content/Device/Include/reg_stm32f4xx.h

Data Fields