Representation of NVIC register. More...

#include <reg_stm32f4xx.h>

Data Fields
volatile uint32_t	ISER0

volatile uint32_t	ISER1

volatile uint32_t	ISER2

uint32_t	RESERVED1 [29]

volatile uint32_t	ICER0

volatile uint32_t	ICER1

volatile uint32_t	ICER2

uint32_t	RESERVED2 [29]

volatile uint32_t	ISPR0

volatile uint32_t	ISPR1

volatile uint32_t	ISPR2

uint32_t	RESERVED3 [29]

volatile uint32_t	ICPR0

volatile uint32_t	ICPR1

volatile uint32_t	ICPR2

uint32_t	RESERVED4 [29]

volatile uint32_t	IABR0

volatile uint32_t	IABR1

volatile uint32_t	IABR2

uint32_t	RESERVED5 [61]

volatile uint8_t	IP [81]

uint8_t	RESERVED6 [3]

uint32_t	RESERVED7 [684]

volatile uint32_t	STIR

Detailed Description

Representation of NVIC register.

Described in programming manual p.193ff.

Field Documentation

◆ IABR0

volatile uint32_t reg_nvic_t::IABR0

Interrupt active bit register 1.

◆ IABR1

volatile uint32_t reg_nvic_t::IABR1

Interrupt active bit register 2.

◆ IABR2

volatile uint32_t reg_nvic_t::IABR2

Interrupt active bit register 3.

◆ ICER0

volatile uint32_t reg_nvic_t::ICER0

Interrupt clear-enable register 1.

◆ ICER1

volatile uint32_t reg_nvic_t::ICER1

Interrupt clear-enable register 2.

◆ ICER2

volatile uint32_t reg_nvic_t::ICER2

Interrupt clear-enable register 3.

◆ ICPR0

volatile uint32_t reg_nvic_t::ICPR0

Interrupt clear-pending register 1.

◆ ICPR1

volatile uint32_t reg_nvic_t::ICPR1

Interrupt clear-pending register 2.

◆ ICPR2

volatile uint32_t reg_nvic_t::ICPR2

Interrupt clear-pending register 3.

◆ IP

volatile uint8_t reg_nvic_t::IP[81]

Interrupt priority.

◆ ISER0

volatile uint32_t reg_nvic_t::ISER0

Interrupt set-enable register 1.

◆ ISER1

volatile uint32_t reg_nvic_t::ISER1

Interrupt set-enable register 2.

◆ ISER2

volatile uint32_t reg_nvic_t::ISER2

Interrupt set-enable register 3.

◆ ISPR0

volatile uint32_t reg_nvic_t::ISPR0

Interrupt set-pending register 1.

◆ ISPR1

volatile uint32_t reg_nvic_t::ISPR1

Interrupt set-pending register 2.

◆ ISPR2

volatile uint32_t reg_nvic_t::ISPR2

Interrupt set-pending register 3.

◆ STIR

volatile uint32_t reg_nvic_t::STIR

Software trigger interrupt register.

The documentation for this struct was generated from the following file:

C:/Temp/Git/CT_Board/Software/Keil/uVision_Pack/Content/Device/Include/reg_stm32f4xx.h

Data Fields