Representation of Timer register. More...

#include <reg_stm32f4xx.h>

Data Fields
volatile uint32_t	CR1

volatile uint32_t	CR2

volatile uint32_t	SMCR

volatile uint32_t	DIER

volatile uint32_t	SR

volatile uint32_t	EGR

volatile uint32_t	CCMR1

volatile uint32_t	CCMR2

volatile uint32_t	CCER

volatile uint32_t	CNT

volatile uint32_t	PSC

volatile uint32_t	ARR

volatile uint32_t	RCR

volatile uint32_t	CCR1

volatile uint32_t	CCR2

volatile uint32_t	CCR3

volatile uint32_t	CCR4

volatile uint32_t	BDTR

volatile uint32_t	DCR

volatile uint32_t	DMAR

volatile uint32_t	OR

Detailed Description

Representation of Timer register.

Described in reference manual p.507ff.

Field Documentation

◆ ARR

volatile uint32_t reg_tim_t::ARR

Auto reload register.

◆ BDTR

volatile uint32_t reg_tim_t::BDTR

Break and dead-time register.

◆ CCER

volatile uint32_t reg_tim_t::CCER

Capture/compare enable register.

◆ CCMR1

volatile uint32_t reg_tim_t::CCMR1

Capture/compare mode register 1.

◆ CCMR2

volatile uint32_t reg_tim_t::CCMR2

Capture/compare mode register 2.

◆ CCR1

volatile uint32_t reg_tim_t::CCR1

Capture/compare register 1.

◆ CCR2

volatile uint32_t reg_tim_t::CCR2

Capture/compare register 2.

◆ CCR3

volatile uint32_t reg_tim_t::CCR3

Capture/compare register 3.

◆ CCR4

volatile uint32_t reg_tim_t::CCR4

Capture/compare register 4.

◆ CNT

volatile uint32_t reg_tim_t::CNT

Count register.

◆ CR1

volatile uint32_t reg_tim_t::CR1

Configuration register 1.

◆ CR2

volatile uint32_t reg_tim_t::CR2

Configuration register 2.

◆ DCR

volatile uint32_t reg_tim_t::DCR

DMA control register.

◆ DIER

volatile uint32_t reg_tim_t::DIER

DMA/interrupt enable register.

◆ DMAR

volatile uint32_t reg_tim_t::DMAR

DMA address for full transfer.

◆ EGR

volatile uint32_t reg_tim_t::EGR

Event generation register.

◆ OR

volatile uint32_t reg_tim_t::OR

Option register.

◆ PSC

volatile uint32_t reg_tim_t::PSC

Prescaler register.

◆ RCR

volatile uint32_t reg_tim_t::RCR

Repetition counter register.

◆ SMCR

volatile uint32_t reg_tim_t::SMCR

Slave mode control register.

◆ SR

volatile uint32_t reg_tim_t::SR

Status register.

The documentation for this struct was generated from the following file:

C:/Temp/Git/CT_Board/Software/Keil/uVision_Pack/Content/Device/Include/reg_stm32f4xx.h

Data Fields