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Timer Compare
Programming Example
The code snippet bellow shows how to configure and use a GPIO pin as input.
#include "reg_stm32f4xx.h" RCC->AHBENR[0] |= (0x1 << 0u); /* Enable GPIOA clock */ RCC->APBENR[0] |= (0x1 << 0u); /* Enable TIM2 clock */ /* configure output */ GPIOA->MODER |= (0x2 << 0u); /* Set pin 0 to Alternate Function */ GPIOA->AFR[0] |= (0x1 << 0u); /* Set pin 0 to AF1 (TIM2) */ /* configure basic timer */ TIM2->PSC = 84000u - 1u; /* Counting with f = 84MHz / 84000 = 1MHz */ TIM2->ARR = 512u; /* Count to 512 */ /* configure timer output */ TIM2->CCMR1 |= (0x6 << 4u); /* Enable PWM mode 1 on channel 1 */ TIM2->CCER |= (0x1 << 0u); /* Enable output on channel 1 */ TIM2->CR1 |= (0x1 << 0u); /* Start timer */
Configuration Registers
CCMR1/2
Capture/compare mode register 1/2
| OCxM | 000 | Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). |
| 001 | Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). | |
| 010 | Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). | |
| 011 | Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. | |
| 100 | Force inactive level - OC1REF is forced low. | |
| 101 | Force active level - OC1REF is forced high. | |
| 110 | PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’). | |
| 111 | PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. | |
| CCxS | 00 | CCx channel is configured as output |
| 01 | CCx channel is configured as input, ICx is mapped on TIx | |
| 10 | CCx channel is configured as input, ICx is mapped on TIx | |
| 11 | CCx channel is configured as input, ICx is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) | |
| *Note: CCxS bits are writable only when the channel is OFF (CCxE = ‘0’ in TIMx_CCER). |
DIER
DMA / Interrupt enable register
| CCxDE | 0 | CCx DMA request disabled (reset state) |
| 1 | CCx DMA request enabled | |
| CCxIE | 0 | CCx interrupt disabled (reset state) |
| 1 | CCx interrupt enabled |
CCER
Capture/compare enable register
| CCxNP | 0 | OC1N active high |
| 1 | OC1N active low | |
| CCxNE | 0 | Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. |
| 1 | On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. | |
| *Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated. | ||
| CCxP | 0 | OC1 active high |
| 1 | OC1 active low | |
| CCxE | 0 | Capture/compare output x disabled (reset state) |
| 1 | Capture/compare output x enabled |
CCRx
Capture/compare enable register
| CCRx | 15:0 | Capture/Compare value |
Legend
