This is an old revision of the document!
Basic Timer
Programming Example
The code snippet bellow shows how to configure and use a GPIO pin as input.
#include "reg_stm32f4xx.h" RCC->APB1ENR |= (0x1 << 0u); /* Enable TIM2 clock. */ /* configure timer */ TIM2->PSC = 84000 - 1; /* Counting with f = 84MHz / 84000 = 1MHz */ TIM2->ARR = 200; /* Count to 200 */ TIM2->CR1 |= (0x1 << 0u); /* Start timer */
Configuration Registers
CR1
Configuration register 1
| DIR* | 0 | Counter used as upcounter (reset state) |
| 1 | Counter used as downcounter | |
| OPM | 0 | Counter is not stopped at update event (reset state) |
| 1 | Counter stops at the next update event | |
| CEN | 0 | Counter disabled (reset state) |
| 1 | Counter enabled |
*This bit is readonly in center-aligned or encoder mode
DIER
DMA / Interrupt enable register
| UDE | 0 | Update DMA request disabled (reset state) |
| 1 | Update DMA request enabled | |
| UIE | 0 | Update interrupt disabled (reset state) |
| 1 | Update interrupt enabled |
SMCR
Slave mode control register
| SMS | 000 | Slave mode disabled (reset state) | 100 | Reset mode |
| 001 | Encoder mode 1 | 101 | Gated mode | |
| 010 | Encoder mode 2 | 110 | Trigger mode | |
| 011 | Encoder mode 3 | 111 | External clock mode 1 | |
| ECE | 0 | External clock mode 2 disabled (reset state) | ||
| 1 | External clock mode 2 enabled. Clock enabled by any active edge on ETRF | |||
PSC
Prescaler register
ARR
Auto reload register
Data Registers
CNT
Count register
Legend
