https://ennis.zhaw.ch/wiki/ 2026-04-28T08:37:28+00:00 https://ennis.zhaw.ch/wiki/ https://ennis.zhaw.ch/wiki/lib/exe/fetch.php?media=wiki:dokuwiki.svg text/html 2022-12-28T08:11:06+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:adc&rev=1672215066&do=diff Analog Digital Converter The ADC of the STM32F429ZI has a 12 bit resolution and up to 19 multiplexed channels. An analog watchdog monitors the input voltage and can take action if necessary. Features * Configurable 12-, 10-, 8- or 6 bit resolution. text/html 2022-12-28T08:14:18+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:dac&rev=1672215258&do=diff Digital Analog Converter The DAC on the STM32F429ZI has 2 channels. Features * Configurable 12- or 8 bit resolution. * Left or right alignment of input data. * External trigger options. * DMA / interrupt support. Configuration Register text/html 2022-12-28T07:50:01+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:dma&rev=1672213801&do=diff Direct Memory Access The two DMA controllers can be used to quickly transfer data between two peripherals (or memory) without any CPU interaction. Not all combinations of peripherals are possible: available DMA connections. Features * 8 streams for each DMA controller, up to 8 channels per stream. text/html 2022-12-28T07:53:21+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:dma_connection&rev=1672214001&do=diff DMA Connections Each DMA controller is connected to the rest of the system in a different way. For memory to memory transfers you should use the DMA controller 2! DMA controller 1 Peripheral Interface On the peripheral interface the following marked peripherals are accessible. text/html 2022-12-28T08:29:22+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:exti&rev=1672216162&do=diff External Interrupts The EXTI controller consists of 23 edge detectors, which can be configured individually. EXTI Lines 0..15EXTI lines 0..15 correspond to the GPIO pins 0..1516PVD interrupt17RTC Alarm A & B interrupt18USB OTG FS interrupt19 text/html 2018-02-23T16:31:35+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:gpio&rev=1519403495&do=diff GPIO Port A..H The STM32F429ZI has a total of 8 GPIO ports (A..H). Each port offers 16 I/O pins (except port H, which offers only 2). Each pin can individually be configured as input, output or be connected to one of the other peripherals (alternate function). text/html 2022-12-28T08:20:41+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:gpio_alternate&rev=1672215641&do=diff Alternate Functions (GPIO) * The output buffer can be enabled (open drain or push-pull). * The output buffer is controlled by connected peripheral. * The Schmitt trigger input is active. * The pull-up and -down resistors are active, according to text/html 2022-12-28T08:18:56+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:gpio_analog&rev=1672215536&do=diff Analog Input (GPIO) * The output buffer is disabled. * The Schmitt trigger input is inactive. * The pull-up and -down resitors are inactive. * Reading IDR returns “0”. Programming Instructions Enable Peripheral Make sure the peripheral is enabled: text/html 2022-12-28T08:15:35+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:gpio_input&rev=1672215335&do=diff General Purpose Input * The output buffer is disabled. * The Schmitt trigger input is active. * The pull-up and -down resistors are active, according to . * Input data is sampled every AHB clock. * Input data register holds I/O state. text/html 2022-12-28T08:17:41+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:gpio_output&rev=1672215461&do=diff General Purpose Output * The is enabled (open drain or push-pull). * The Schmitt trigger input is active. * The pull-up and -down resistors are active, according to . * Input data is sampled every AHB clock. * Input data register holds I/O state. text/html 2016-10-03T09:43:53+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:interrupt_table&rev=1475487833&do=diff Interrupt Table IRQ Priority Address -3* Reset 0x0000'0004 -2* NMI 0x0000'0008 Non maskable interrupt -1* HardFault 0x0000'000c 0 MemManage 0x0000'0010 MPU missmatch 1 BusFault 0x0000'0014 Prefetch fault, memory access fault text/html 2022-12-27T18:53:23+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:nvic&rev=1672167203&do=diff Nested Vectored Interrupt Controller (NVIC) The NVIC manages all the interrupts and is closely coupled to the processor core. A list of all available interrupts: interrupt table. Features * 91 maskable interrupt channels. * 16 programmable priority levels. text/html 2022-12-27T18:58:56+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:pwr&rev=1672167536&do=diff Power Controller The STM32F429ZI requires a voltage supply VDD of 1,8..3,6 V to operate. A linear voltage regulator is used to generate the 1,2 V internally needed for the CPU. The real time clock, backup registers and backup RAM can be powered by V text/html 2019-09-16T07:19:43+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:pwr_sleep&rev=1568618383&do=diff SLEEP Mode In SLEEP mode only the cpu clock is disabled, everything else stays as previously configured. Enter SLEEP mode * WFI (wait for interrupt) instuction enters SLEEP mode. Exit SLEEP mode * Clear the EXTI (and, if not EXTI, the corresponding NVIC) pending bit. text/html 2022-12-27T19:00:48+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:pwr_stop&rev=1672167648&do=diff STOP Mode In STOP mode only the cpu clock is disabled, everything else stays as previously configured. Enter STOP mode * WFI (wait for interrupt) instruction with SLEEPDEEP bit set enters STOP mode. Exit STOP mode * Clear the EXTI (and, if not EXTI, the corresponding NVIC) pending bit. text/html 2019-09-16T07:23:39+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:pwr_stop_new&rev=1568618619&do=diff STOP Mode In STOP mode only the cpu clock is disabled, everything else stays as previously configured. Enter STOP mode * WFI (wait for interrupt) instuction enters SLEEP mode. Exit STOP mode * Clear the EXTI (and, if not EXTI, the corresponding NVIC) pending bit. text/html 2022-12-27T19:28:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:rcc&rev=1672169326&do=diff Reset and Clock Control (RCC) These registers allow to configure the system clock and enable / disable peripherals. * RCC Setup System Clocks * RCC Enable/disable clocks for peripherals and reset peripherals text/html 2022-12-27T19:27:55+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:rcc_clock&rev=1672169275&do=diff RCC Setup System Clocks To setup the system clocks you have to: * Select a . * Set up the (optional). * Configure the . Available Oscillators ftypicalLSI32 kHzLow speed internal oscillatorLSE32 kHzLow speed external oscillatorHSI16 MHzHigh speed internal oscillator text/html 2022-12-27T19:24:20+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:rcc_peripherals&rev=1672169060&do=diff RCC Enable/disable clocks for peripherals and reset peripherals The peripherals can be controlled by the following 3 register sets: * The enable or disable the clocks for the peripherals. * The enable or disable the clocks for the peripherals in sleep mode. text/html 2022-12-27T17:55:17+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:rtc&rev=1672163717&do=diff Real Time Clock (RTC) The RTC is an independent BCD timer/counter. It provides a time-of-day clock/calendar, two programmable alarms and a programmable periodic wake up timer. Features * Time-of-day clock/calendar with subseconds, seconds, minutes, hours (12h/24h format), day (day of week), date (day of month), month, and year text/html 2022-12-27T17:59:18+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:rtc_real_time_clock&rev=1672163958&do=diff RTC Real-time Clock and Calendar Time-of-day clock/calendar with subseconds, seconds, minutes, hours (12h/24h format), day (day of week), date (day of month), month, and year. RTC_DR - RTC Date Register DU[3:0]Date units in BCD formatDT[1:0] text/html 2022-12-27T18:42:19+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:rtc_wakeup&rev=1672166539&do=diff Wake Up Timer The wakeup timer is a programmable 16 bit auto-reload down-counter. The wakeup timer range can be extended to 17 bits. The wakeup timer can be used to generate a periodic interrupt through the wakeup timer flag (WUTF). Additionally the WUTF flag can be output (through signals WKUP, RTC_ALARM and on to RTC_AF1) to pin PC13. text/html 2022-12-28T08:36:40+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:spi&rev=1672216600&do=diff SPI / I²S 1..6 The SPI interface offers 2 main functions: SPI and I²S (audio protocol). There are a total of 6 SPI controllers which can be configured and used independently. Features * Full-duplex synchronous transfer (on 3 lines: MOSI, MISO, SCK). text/html 2022-12-27T17:53:43+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:systick&rev=1672163623&do=diff System Tick Timer The STM32F429ZI offers a 24 bit system tick timer. It is a simple down counter. The system tick timer counts down from the reload value to zero and generates an interrupt. Registers CTRL - Control and status register text/html 2023-02-08T12:57:45+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:timer&rev=1675861065&do=diff Timer 2..5 The STM32F429ZI offers several general purpose timers. Timer 2 and 5 are 32 bit timers, while timer 3 and 4 are 16 bit timers. They may be used for measuring time (basic timer), measuring input pulse length (input capturing) or generating waveforms (output compare / PWM). The timers are fully independent and can be synchronized together. text/html 2023-10-19T09:49:25+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:timer_base&rev=1697708965&do=diff Basic Timer Configuration Registers TIMx_CR1 - Configuration register 1 DIR*0Counter used as upcounter (reset state)1Counter used as downcounterOPM0Counter is not stopped at update event (reset state)1Counter stops at the next update event text/html 2022-12-28T07:56:11+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:timer_clock&rev=1672214171&do=diff Timer Clock Source Configuration Registers TIMx_CR1 - Configuration register 1 CKD00tDTS => tCKINT01tDTS => 2 · tCKINT10tDTS => 4 · tCKINT11Reserved TIMx_SMCR - Slave mode control register ETP0ETR is noninverted, active at high level or rising edge (reset state) text/html 2022-12-28T08:00:45+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:timer_compare&rev=1672214445&do=diff Timer Compare Configuration Registers TIMx_CCMR1/2 - Capture/compare mode register 1/2 Output compare mode OCxM000Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). text/html 2022-12-28T08:39:48+00:00 Anonymous (anonymous@undisclosed.example.com) https://ennis.zhaw.ch/wiki/doku.php?id=stm32:peripherals:usart&rev=1672216788&do=diff Universal Asynchronous Receiver Transmitter The UART offers a very flexible, full-duplex, industrial standard, serial receiver / transmitter. Including IrDA and modem operations (CTS/RTS). Features * Full-, half-duplex communication. *