Timer Compare







Output compare mode

OCxM000Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
001Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100Force inactive level - OC1REF is forced low.
101Force active level - OC1REF is forced high.
110PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
111PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.

Input compare mode

ICxF0000No filter, fDTS (reset state)1000fsampling ⇒ fDTS / 8, N=6
0001fsampling ⇒ fCKINT, N=21001fsampling ⇒ fDTS / 8, N=8
0010fsampling ⇒ fCKINT, N=41010fsampling ⇒ fDTS / 16, N=5
0011fsampling ⇒ fCKINT, N=81011fsampling ⇒ fDTS / 16, N=6
0100fsampling ⇒ fDTS / 2, N=61100fsampling ⇒ fDTS / 16, N=8
0101fsampling ⇒ fDTS / 2, N=81101fsampling ⇒ fDTS / 32, N=5
0110fsampling ⇒ fDTS / 4, N=61110fsampling ⇒ fDTS / 32, N=6
0111fsampling ⇒ fDTS / 4, N=81111fsampling ⇒ fDTS / 32, N=8
ICxPSC00no prescaler, capture is done each time an edge is detected on the capture input (reset state)
01 capture is done once every 2 events
10 capture is done once every 4 events
11 capture is done once every 8 events

Select mode

CCxS00CCx channel is configured as output
01CCx channel is configured as input, ICx is mapped on TIx
10CCx channel is configured as input, ICx is mapped on TIx
11CCx channel is configured as input, ICx is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
*Note: CCxS bits are writable only when the channel is OFF (CCxE = ‘0’ in TIMx_CCER).




CCxDE0CCx DMA request disabled (reset state)
1CCx DMA request enabled
CCxIE0CCx interrupt disabled (reset state)
1CCx interrupt enabled




CCxNP0OC1N active high
1OC1N active low
CCxNE0Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
1On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
*Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated.
CCxP0OC1 active high
1OC1 active low
CCxE0Capture/compare output x disabled (reset state)
1Capture/compare output x enabled




CCRx15:0Capture/Compare value




MOE0OC and OCN outputs are disabled or forced to idle state. (reset state)
1 OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register).

The code snippet below shows how to configure and use a GPIO pin as input.

#include "reg_stm32f4xx.h"
 
RCC->AHBENR[0] |= (0x1 << 0u);          /* Enable GPIOA clock */
RCC->APBENR[0] |= (0x1 << 0u);          /* Enable TIM2 clock */
 
/* configure output */
GPIOA->MODER |= (0x2 << 0u);          /* Set pin 0 to Alternate Function */
GPIOA->AFR[0] |= (0x1 << 0u);         /* Set pin 0 to AF1 (TIM2) */
 
/* configure basic timer */
TIM2->PSC = 84000u - 1u;              /* Counting with f = 84MHz / 84000 = 1MHz */
TIM2->ARR = 512u;                     /* Count to 512 */
 
/* configure timer output */
TIM2->CCMR1 |= (0x6 << 4u);           /* Enable PWM mode 1 on channel 1 */
TIM2->CCER |= (0x1 << 0u);            /* Enable output on channel 1 */
 
TIM2->CR1 |= (0x1 << 0u);             /* Start timer */


  • stm32/peripherals/timer_compare.txt
  • Last modified: 2022/12/28 08:00
  • by ruan