Basic Timer







DIR*0Counter used as upcounter (reset state)
1Counter used as downcounter
OPM0Counter is not stopped at update event (reset state)
1Counter stops at the next update event
CEN0Counter disabled (reset state)
1Counter enabled

*This bit is readonly in center-aligned or encoder mode




UDE0Update DMA request disabled (reset state)
1Update DMA request enabled
CC1IE0CC1 interrupt disabled (reset state)
1CC1 interrupt enabled
UIE0Update interrupt disabled (reset state)
1Update interrupt enabled




ECE0External clock mode 2 disabled (reset state)
1External clock mode 2 enabled. Clock enabled by any active edge on ETRF
ETF0000No filter, fDTS (reset state)1000fsampling ⇒ fDTS / 8, N=6
0001fsampling ⇒ fCKINT, N=21001fsampling ⇒ fDTS / 8, N=8
0010fsampling ⇒ fCKINT, N=41010fsampling ⇒ fDTS / 16, N=5
0011fsampling ⇒ fCKINT, N=81011fsampling ⇒ fDTS / 16, N=6
0100fsampling ⇒ fDTS / 2, N=61100fsampling ⇒ fDTS / 16, N=8
0101fsampling ⇒ fDTS / 2, N=81101fsampling ⇒ fDTS / 32, N=5
0110fsampling ⇒ fDTS / 4, N=61110fsampling ⇒ fDTS / 32, N=6
0111fsampling ⇒ fDTS / 4, N=81111fsampling ⇒ fDTS / 32, N=8
TS 000Internal Trigger 0 (ITR0) (reset state)100 TI1 Edge Detector (TI1F_ED)
001Internal Trigger 1 (ITR1)101Filtered Timer Input 1 (TI1FP1)
010Internal Trigger 2 (ITR2)110 Filtered Timer Input 2 (TI2FP2)
011Internal Trigger 3 (ITR3)111External Trigger input (ETRF)
SMS000Slave mode disabled (reset state)100Reset mode
001Encoder mode 1101Gated mode
010Encoder mode 2110Trigger mode
011Encoder mode 3111External clock mode 1










The code snippet below shows how to configure and use a timer.

#include "reg_stm32f4xx.h"
 
RCC->APB1ENR |= (0x1 << 0u);          /* Enable TIM2 clock. */
 
/* configure timer */
TIM2->PSC = 0u;              /* Counting with f = 84MHz / 1 = 84MHz */
TIM2->ARR = 84000u - 1u;                     /* Count to 84000 */
 
TIM2->CR1 |= (0x1 << 0u);             /* Start timer */


  • stm32/peripherals/timer_base.txt
  • Last modified: 2023/10/19 09:49
  • by frtt