RCC Enable/disable clocks for peripherals and reset peripherals
The peripherals can be controlled by the following 3 register sets:
- The RCC_xxxxENR - Peripheral clock enable registers enable or disable the clocks for the peripherals.
- The RCC_xxxxLPENR Low power clock enable registers enable or disable the clocks for the peripherals in sleep mode.
- The RCC_xxxxRSTR - Peripheral reset registers can reset a peripheral.
Configuration Registers
AHB1xxx - AHB1ENR, AHB1LPENR and AHB1RSTR registers
AHB2xxx - AHB2ENR, AHB2LPENR and AHB2RSTR registers
AHB3xxx - AHB3ENR, AHB3LPENR and AHB3RSTR registers
APB1xxx - APB1ENR, APB1LPENR and APB1RSTR registers
APB2xxx - APB2ENR, APB2LPENR and APB2RSTR registers
Register Description
RCC_xxxxENR - Peripheral clock enable registers
| zEN | 0 | Peripheral clock disabled |
| zEN | 1 | Peripheral clock enabled |
RCC_xxxxLPENR Low power clock enable registers
| zLPEN | 0 | Peripheral clock disabled during sleep mode |
| zLPEN | 1 | Peripheral clock enabled during sleep mode |
RCC_xxxxRSTR - Peripheral reset registers
| zLPEN | 0 | Peripheral not reset |
| zLPEN | 1 | Resets peripheral |