This is an old revision of the document!


External Interrupts

The EXTI controller consists of 23 edge detectors, which can be configured individually.




0..15EXTI lines 0..15 correspond to the GPIO pins 0..15
16PVD interrupt
17RTC Alarm A & B interrupt
18USB OTG FS interrupt
19Ethernet wakeup
20USB OTG HS interrupt
21Tamper & time stamp interrupt
22RTC wakeup interrupt


#include "reg_stm32f4xx.h"
#include "reg_stm32f4xx.h"
 
RCC->AHBENR[0] |= (0x1 << 0u);    /* Enable GPIOA clock */
 
/* Configure GPIO pin A.10 as input. */
GPIOA->MODER &= ~(0x3 << 10u);    /* Clear existing mode bits 10 and 11. */
 
GPIOA->PUPDR &= ~(0x3 << 10u);    /* Clear existing pull-up/-down bits 10 and 11. */
GPIOA->PUPDR |= (0x1 << 10u);     /* Set pin 5 to pull-up mode. */


To choose which GPIO peripheral should trigger EXTI5 you have to configure the SYSCFG register.

#include "reg_stm32f4xx.h"
 
SYSCFG->EXTICR[1] |= (0x0 << 4u);  /* Set EXTI5 to GPIOA. */


#include "reg_stm32f4xx.h"
 
EXTI->RTSR |= (0x1 << 5u);         /* Trigger on rising edge. */
EXTI->IMR |= (0x1 << 5u);          /* Unmask interrupt line. */


#include "reg_stm32f4xx.h"
 
NVIC->ISER[0] |= (0x1 << 23u);     /* Enable EXTI5 interrupt. */


EXTICR1

External interrupt configuration register 1




EXTICR2

External interrupt configuration register 2




EXTICR3

External interrupt configuration register 3




EXTICR4

External interrupt configuration register 4




EXTICRx0000GPIOA pin x (reset state)
0001GPIOB pin x
1010GPIOK pin x


Interrupt clear enable register




CLRENA*1Disable interrupt (mask interrupt)

*Setting this bit to 0 has no effect, refer to ISER

  • stm32/peripherals/exti.1475754130.txt.gz
  • Last modified: 2016/10/06 11:42
  • by feur