Direct Memory Access

The two DMA controller can be used to quickly transfer data between two peripherals (or memory) without any CPU interaction.
Not all combination of peripherals are possible: available DMA connections.

• 8 streams for each DMA controller, up to 8 channels per stream.
• 4 (32 bit wide) FIFO buffer per stream.
• Programmable priority.

The code snippet bellow shows how to configure and use the DMA controller.

#include "reg_stm32f4xx.h"
 
RCC->AHBENR[0] |= (0x1 << 22u);      /* Enable DMA2 clock */
 
/* Configure DMA2 controller. */
DMA2->STREAM[0].CR |= (2u << 25u);   /* Setup channel. */
DMA2->STREAM[0].CR |= (0x0 << 6u);   /* Setup direction. */
DMA2->STREAM[0].CR |= (0x1 << 8u);   /* Setup circular mode. */
DMA2->STREAM[0].NDTR |= 1u;          /* Setup nr of transfers. */
 
/* Setup source and destination. */
DMA2->STREAM[0].PAR |= (uint32_t) &(ADC3->DR);
DMA2->STREAM[0].M0AR |= (uint32_t) &(TIM3->CCR[0]);
 
/* Setup buffer size. */
DMA2->STREAM[0].CR |= (0x1 << 11u);  /* PSIZE */
DMA2->STREAM[0].CR |= (0x1 << 13u);  /* MSIZE */
 
/* Start DMA transfer. */
DMA2->STREAM[0].CR |= (0x1 << 0u);

Hardware Abstraction Layer
Register Types
InES DMA HAL Interface

Stream X configuration register

* Only writeable if EN = '0'

Stream X peripheral address register

Stream X memory 0 address register

Stream X memory 1 address register

Stream X number of data register