Basic Timer

Configuration Registers

TIMx_CR1 - Configuration register 1

DIR*	0	Counter used as upcounter (reset state)
DIR*	1	Counter used as downcounter
OPM	0	Counter is not stopped at update event (reset state)
OPM	1	Counter stops at the next update event
CEN	0	Counter disabled (reset state)
CEN	1	Counter enabled

*This bit is readonly in center-aligned or encoder mode

TIMx_DIER - DMA / Interrupt enable register

UDE	0	Update DMA request disabled (reset state)
UDE	1	Update DMA request enabled
CC1IE	0	CC1 interrupt disabled (reset state)
CC1IE	1	CC1 interrupt enabled
UIE	0	Update interrupt disabled (reset state)
UIE	1	Update interrupt enabled

TIMx_SMCR - Slave mode control register

ECE	0	External clock mode 2 disabled (reset state)
ECE	1	External clock mode 2 enabled. Clock enabled by any active edge on ETRF
ETF	0000	No filter, f_DTS (reset state)	1000	f_sampling ⇒ f_DTS / 8, N=6
	0001	f_sampling ⇒ f_CKINT, N=2	1001	f_sampling ⇒ f_DTS / 8, N=8
	0010	f_sampling ⇒ f_CKINT, N=4	1010	f_sampling ⇒ f_DTS / 16, N=5
	0011	f_sampling ⇒ f_CKINT, N=8	1011	f_sampling ⇒ f_DTS / 16, N=6
	0100	f_sampling ⇒ f_DTS / 2, N=6	1100	f_sampling ⇒ f_DTS / 16, N=8
	0101	f_sampling ⇒ f_DTS / 2, N=8	1101	f_sampling ⇒ f_DTS / 32, N=5
	0110	f_sampling ⇒ f_DTS / 4, N=6	1110	f_sampling ⇒ f_DTS / 32, N=6
	0111	f_sampling ⇒ f_DTS / 4, N=8	1111	f_sampling ⇒ f_DTS / 32, N=8
TS	000	Internal Trigger 0 (ITR0) (reset state)	100	TI1 Edge Detector (TI1F_ED)
	001	Internal Trigger 1 (ITR1)	101	Filtered Timer Input 1 (TI1FP1)
	010	Internal Trigger 2 (ITR2)	110	Filtered Timer Input 2 (TI2FP2)
	011	Internal Trigger 3 (ITR3)	111	External Trigger input (ETRF)
SMS	000	Slave mode disabled (reset state)	100	Reset mode
	001	Encoder mode 1	101	Gated mode
	010	Encoder mode 2	110	Trigger mode
	011	Encoder mode 3	111	External clock mode 1

TIMx_PSC - Prescaler register

TIMx_ARR - Auto reload register

Data Registers

TIMx_CNT - Count register

Programming Example

The code snippet below shows how to configure and use a timer.

#include "reg_stm32f4xx.h"
 
RCC->APB1ENR |= (0x1 << 0u);          /* Enable TIM2 clock. */
 
/* configure timer */
TIM2->PSC = 0u;              /* Counting with f = 84MHz / 1 = 84MHz */
TIM2->ARR = 84000u - 1u;                     /* Count to 84000 */
 
TIM2->CR1 |= (0x1 << 0u);             /* Start timer */