SPI / I²S 1..6

The SPI interface offers 2 main functions: SPI and I²S (audio protocol).
There are a total of 6 SPI controllers which can be configured and used independently.

Features

Full-duplex synchronous transfer (on 3 lines: MOSI, MISO, SCK).
Simplex synchronous transfer (on 2 lines: MOSI/MISO, SCK).
8 or 16 bit data transfer width.
Master or slave mode.
Slave select either by hardware or software.
Interrupt, CRC and DMA support.

Configuration Registers

SPI_CR1 - Configuration register 1

(not used in I²S mode)

MSTR	0	Slave mode (reset state)
	1	Master mode
BR	000	BR ⇒ f_PCLK2 / 2 (reset state)	100	BR ⇒ f_PCLK2 / 32
	001	BR ⇒ f_PCLK2 / 4	101	BR ⇒ f_PCLK2 / 64
	010	BR ⇒ f_PCLK2 / 8	110	BR ⇒ f_PCLK2 / 128
	011	BR ⇒ f_PCLK2 / 16	111	BR ⇒ f_PCLK2 / 256
SPE	0	SPI disabled (reset state)
	1	SPI enabled
LSBFIRST	0	MSB transmitted first (reset state)
	1	LSB transmitted first
SSM	0	Slave management by hw (reset state)
	1	Slave management by sw
DFF	0	Data frame: 8 bit (reset state)
	1	Data frame: 16 bit

SPI_CR2 - Configuration register 2

SSOE	0	Slave select disabled in master mode (reset state)
SSOE	1	Slave select enabled in master mode (not for multi master setup)
FRF	0	Motorolla frame format (reset state)
FRF	1	Texas Instruments frame format
ERRIE	0	Error interrupt disabled (reset state)
ERRIE	1	Error interrupt enabled
RXNEIE	0	RX not empty interrupt disabled (reset state)
RXNEIE	1	RX not empty interrupt enabled
TXEIE	0	TX empty interrupt disabled (reset state)
TXEIE	1	TX empty interrupt enabled

SPI_CRCPR - CRC polynomial register

(not used in I²S mode)

Contains polynomial used to calculate CRC. Reset value: 0x0007.

SPI_RXCRCR - RX CRC register

(not used in I²S mode)

Contains computed CRC value of received bytes.

SPI_TXCRCR - TX CRC register

(not used in I²S mode)

Contains computed CRC value of transmitted bytes.

SPI_I2SCFGR - I²S configuration register

(not used in SPI mode)

SPI_I2SPR - I²S prescaler register

(not used in SPI mode)

Data Register

SPI_DR - Data register

Data received or to be transmitted. Split into 2 buffers:

Writing to DR writes to TX Buffer.
Reading from DR reads from RX Buffer.

Programming Example

The code snippet bellow shows how to configure and use the SPI peripheral.

#include "reg_stm32f4xx.h"
 
RCC->AHBENR[0] |= (0x1 << 0u);       /* Enable GPIOA clock */
RCC->APBENR[1] |= (0x1 << 12u);      /* Enable SPI1 clock */
 
/* Configure GPIO pin A.4 to A.7 in alternate function mode. */
GPIOA->MODER &= ~(0xff << 8u);       /* Clear existing mode bits 8 to 15. */
GPIOA->MODER |= (0xaa << 8u);        /* Set pin 4..7 to alternate function mode. */
 
GPIOA->OSPEEDR &= ~(0xff << 8u);     /* Clear existing output speed bits 8 to 15. */
GPIOA->OSPEEDR |= (0xff << 8u);      /* Set pin 4..7 to high speed (100MHz) mode. */
 
GPIOA->AFR[0] &= ~(0xffff << 16u);   /* Clear existing af bits 16 to 31. */
GPIOA->AFR[0] |= (0x5555 << 16u);    /* Set pin 4..7 to AF5 (SPI1). */
 
/* Configure SPI1 in slave mode. */
SPI1->CR1 = 0u;                      /* Reset SPI1 configuration. */
SPI1->CR2 = 0u;                      /* Reset SPI1 configuration. */
 
SPI1->CR1 |= (0x1 << 3u) |           /* Select 11,25MHz as baudrate (45 MHz / 4). */
             (0x1 << 6u);            /* Enable SPI. */