====== Universal Asynchronous Receiver Transmitter ======

The UART offers a very flexible, full-duplex, industrial standard, serial receiver / transmitter. \\
Including IrDA and modem operations (CTS/RTS). \\

\\ {{usart_complete.svg}} \\ \\

===== Features =====

  * Full-, half-duplex communication.
  * Fractional baud rate generator.
  * 8- and 9 bit word length.
  * DMA and interrupt support.
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===== Configuration Registers =====

==== USART_CR1 - Configuration register 1 ====

\\ {{usart_reg_cr1.svg}} \\ \\

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|RE|0|Receiver disable (reset state)|
|:::|1|Receiver enable|
|TE|0|Transmitter disable (reset state)|
|:::|1|Transmitter enable|
|RXNEIE|0|Receiver not empty interrupt disable (reset state)|
|:::|1|Receiver not empty interrupt enable|
|TCIE|0|Transmission complete interrupt disable (reset state)|
|:::|1|Transmission complete enable|
|TXEIE|0|Transmitter empty interrupt disable (reset state)|
|:::|1|Transmitter empty interrupt enable|
|M|0|8 data bits (reset state)|
|:::|1|9 data bits enable|
|UE|0|USART disable (reset state)|
|:::|1|USART enable|
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==== USART_CR2 - Configuration register 2 ====

\\ {{usart_reg_cr2.svg}} \\ \\

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|STOP|00| 1 stop bit (reset state)|
|:::|01| 0,5 stop bit|
|:::|10| 2 stop bit|
|:::|11| 1,5 stop bit|
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==== USART_BRR - Baud rate register ====

\\ {{usart_reg_brr.svg}} \\ \\

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|Fraction|x|Defines fraction of PCLK divider|
|Mantissa|x|Defines Mantissa of the PCLK divider|
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===== Status Register =====

==== USART_SR -  Status register ====

\\ {{usart_reg_sr.svg}} \\ \\

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|RXNE|0|Data is not received|
|:::|1|Received data is ready to be read|
|TC|0|Transmission **not** complete|
|:::|1|Transmission complete|
|TXE|0|Data is **not** transferred to the shift register|
|:::|1|Data transferred to the shift register|
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===== Data Register =====

==== USART_DR - Data register ====

\\ {{usart_reg_dr.svg}} \\ \\

  * Reading from DR register reads from RXDR Buffer.
  * Writing to DR register writes to TXDR Buffer.
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===== Programming Example =====

==== Setup GPIO ====

<code c>
#include "reg_stm32f4xx.h"

RCC->AHBENR[0] |= (0x1 << 0u);       /* Enable GPIOA clock */

/* Configure GPIO pin A.0 and A.1 in alternate function mode. */
GPIOA->MODER &= ~(0xf << 0u);        /* Clear existing mode bits 0 to 3. */
GPIOA->MODER |= (0xa << 0u);         /* Set pin 0..1 to alternate function mode. */

GPIOA->OSPEEDR &= ~(0xff << 0u);     /* Clear existing output speed bits 0 to 3. */
GPIOA->OSPEEDR |= (0xff << 0u);      /* Set pin 0..1 to high speed (100MHz) mode. */

GPIOA->AFR[0] &= ~(0xff << 0u);      /* Clear existing af bits 0 to 7. */
GPIOA->AFR[0] |= (0x88 << 0u);       /* Set pin 0..1 to AF8 (UART4). */
</code>
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==== Transmitting Data ====

<code c>
#include "reg_stm32f4xx.h"

RCC->APBENR[0] |= (0x1 << 19u);      /* Enable UART4 clock */

UART4->CR1 |= (0x1 << 13u);          /* Enable UART */
UART4->BRR |= (42000000 / 115200);   /* Set baudrate to 115'200 */

UART4->CR1 |= (0x1 << 3u);           /* Enable transmission */
UART4->DR = data_send[0];            /* Send first data */
while(!(UART4->SR & (0x1 << 7u)));   /* Wait til TXE flag is set */
UART4->DR = data_send[1];            /* Send first data */
while(!(UART4->SR & (0x1 << 7u)));   /* Wait til TXE flag is set */
UART4->DR = data_send[2];            /* Send last data */
while(!(UART4->SR & (0x1 << 6u)));   /* Wait til TC flag is set */
</code>
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==== Receiving Data ====

<code c>
#include "reg_stm32f4xx.h"

RCC->APBENR[0] |= (0x1 << 19u);      /* Enable UART4 clock */

UART4->CR1 |= (0x1 << 13u);          /* Enable UART */
UART4->BRR |= (42000000 / 115200);   /* Set baudrate to 115'200 */

UART4->CR1 |= (0x1 << 2u);           /* Enable receiver */
while(!(UART4->SR & (0x1 << 5u)));   /* Wait til RXNE flag is set */
data_received = UART4->DR            /* Read data */
</code>
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