====== Wake Up Timer ======

The wakeup timer is a programmable 16 bit auto-reload down-counter. \\
The wakeup timer range can be extended to 17 bits. \\

\\ {{rtc_timer.svg?700em}} \\ \\

The wakeup timer can be used to generate a periodic interrupt through the wakeup timer flag (WUTF). Additionally the WUTF flag can be output (through signals WKUP, RTC_ALARM and on to RTC_AF1) to pin PC13.

The wakeup timer clock input can be
  * RTCCLK (usually 32.768 kHz) divided by 2, 4, 8 or 16. \\ As a result this allows wakeup interrupt periods from 122 us to 32 s, with a resolution down to 61 us.
  * ck_spre (usually 1 Hz internal clock). \\ As a result this allows wakeup interrupt periods from 1 s to around 36 hours.
===== Programming Instructions =====

==== RTC register write protection ====

After a reset the backup domain is write protected. The backup domain encompasses: RTC, LSE oscillator, backup SRAM, I/O pins PC13 to PC15 and PI8. The backup domain is powered through VBAT even if VDD is turned off.\\
Unlock access to backup domain:
  * Set the ''DBP'' bit (disable backup protection) in ''PWR->CR''.

After a backup domain reset (not a system reset) most of the RTC registers are write protected. \\
Disable the write protection by writing the unlock key to ''RTC->WPR'':
  * Write ''0xCA'' to ''RTC->WPR''.
  * Write ''0x53'' to ''RTC->WPR''.

==== Enable RTC clock ====

The RTC clock is disabled by default. Select a clock source and enable the RTC clock. \\
Make sure that the clock source is available while in [[pwr#low_power_modes|power down]] mode.
  * Setup / enable an appropriate [[rcc_clock#clock_source|clock source]], e.g. LSI.
  * Select clock source for RTCCLK in ''RCC->BDCR''.
  * Enable RTCCLK in ''RCC->BDCR''.

==== Setup wakeup timer ====

To configure the auto wakeup timer proceed as follows:
  * Disable wakeup timer in ''RTC->CR''.
  * Wait until configuration of RTC is allowed. \\ Check corresponding bit in ''RTC->ISR''.
  * Program prescaler value in ''RTC->CR''.
  * Program reload value in ''RTC->WUTR''.
  * Enable wakeup interrupt in ''RTC->CR''.

To use the wakeup interrupt, you need to configure the EXTI channel \\
and enable it in the NVIC:
  * Clear any pending wakeup interrupt flag in ''RTC->ISR''.
  * Configure the dedicated [[exti|EXTI interrupt]] channel for the RTC. \\ I.e. select edge and enable.
  * Enable the RTC wakeup interrupt in the [[nvic|NVIC]].

Start the wakeup timer:
  * Enable wakeup timer in ''RTC->CR''.

Reenable RTC write protection:
  * Write ''0xff'' to ''RTC->WPR''.
\\

===== Configuration Registers =====

==== RTC_CR - Configuration register ====

\\ {{rtc_reg_cr.svg}} \\ \\

|< 100% 5em 5em 20em 5em >|
|WUCKSEL|000|f<sub>WUT</sub> => RTCCLK/16 (reset state)|10x|f<sub>WUT</sub> => ck_spre (1Hz)|
|:::|001|f<sub>WUT</sub> => RTCCLK/8|:::|:::|
|:::|010|f<sub>WUT</sub> => RTCCLK/4|11x|f<sub>WUT</sub> => ck_spre (1Hz), 2<sup>16</sup> added to WUTR|
|:::|011|f<sub>WUT</sub> => RTCCLK/2|:::|:::|
|WUTE|0|Wake up timer disabled (reset state)||
|:::|1|Wake up timer enabled||
|WUTIE|0|Wake up timer interrupt disabled (reset state)||
|:::|1|Wake up timer interrupt enabled||

==== RTC_WUTR - Wakeup timer register ====

\\ {{rtc_reg_wutr.svg}} \\ \\


===== Status Registers =====

==== RTC_ISR - Initialization and status register ====

\\ {{rtc_reg_isr.svg}} \\ \\

|< 100% 5em 5em >|
|WUTWF*|0|Wake up timer configuration not allowed|
|:::|1|Wake up timer configuration allowed|
|WUTF||Wake up timer flag is set by hardware when wakeup counter reaches 0 and cleared by software by writing 0.||
* This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware.

===== Back domain control register =====

==== RCC_BDCR - Back domain control register ====

\\ {{rcc_reg_bdcr.svg}} \\ \\ 

|< 100% 5em 5em >|
|RTCEN*|0|RTC clock disabled|
|:::|1|RTC clock enabled|
|RTCSEL|00|No clock|
|:::|01|LSE oscillator clock used as the RTC clock|
|:::|10|LSI oscillator clock used as the RTC clock|
|:::|11|HSE oscillator clock divided by a programmable prescaler(selection Through RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC clock|