====== RCC Enable/disable clocks for peripherals and reset peripherals ======

The peripherals can be controlled by the following 3 register sets:
  * The [[#RCC_xxxxENR - Peripheral clock enable registers]] enable or disable the clocks for the peripherals.
  * The [[#RCC_xxxxLPENR Low power clock enable registers]] enable or disable the clocks for the peripherals in sleep mode.
  * The [[#RCC_xxxxRSTR - Peripheral reset registers]] can reset a peripheral.

\\ {{clock_peripherals.svg}} \\ \\


===== Configuration Registers =====
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==== AHB1xxx - AHB1ENR, AHB1LPENR and AHB1RSTR registers ====

\\ {{clock_reg_ahb1_r.svg}} \\ \\

==== AHB2xxx - AHB2ENR, AHB2LPENR and AHB2RSTR registers ====

\\ {{clock_reg_ahb2_r.svg}} \\ \\

==== AHB3xxx - AHB3ENR, AHB3LPENR and AHB3RSTR registers ====

\\ {{clock_reg_ahb3_r.svg}} \\ \\

==== APB1xxx - APB1ENR, APB1LPENR and APB1RSTR registers ====

\\ {{clock_reg_apb1_r.svg}} \\ \\

==== APB2xxx - APB2ENR, APB2LPENR and APB2RSTR registers ====

\\ {{clock_reg_apb2_r.svg}} \\ \\

===== Register Description =====
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==== RCC_xxxxENR - Peripheral clock enable registers ====

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|zEN|0|Peripheral clock disabled|
|zEN|1|Peripheral clock enabled|

==== RCC_xxxxLPENR Low power clock enable registers ====

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|zLPEN|0|Peripheral clock disabled during sleep mode|
|zLPEN|1|Peripheral clock enabled during sleep mode|

==== RCC_xxxxRSTR - Peripheral reset registers ====

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|zLPEN|0|Peripheral **not** reset|
|zLPEN|1|Resets peripheral|