Differences

This shows you the differences between two versions of the page.

--- stm32:peripherals:timer_output [2016/06/27 11:27] – created feur
+++ stm32:peripherals:timer_output [2016/06/28 11:55] (current) – removed feur
@@ Line 1: / Line 1: @@
-====== Timer Output ======
-\\ {{timer_base.svg}} \\ \\
-== Configuration Registers ==
-|< 100% 10em >|
-|[[#registers|CR1]]|Control Register 1|
-|[[#registers|PSC]]|Prescaler register|
-|[[#registers|ARR]]|Auto reload register|
-|[[#registers|DIER]]|DMA / Interrupt enable register|
-== Data Registers ==
-|< 100% 10em >|
-|[[#registers|CNT]]|Counting register|
-=== Upcounting ===
-=== Downcounting ===
-=== Up/Down counting ===
-==== Clock Source ====
-\\ {{timer_clock.svg}} \\ \\
-==== Output Compare ====
-\\ {{timer_output.svg}} \\ \\
-===== Registers =====
-==== Configuration Registers ====
-=== CR1 ===
-\\ {{timer_reg_cr1.svg}} \\ \\
-|< 100% 5em 5em >|
-|DIR|0|Counter used as upcounter|
-|:::|1|Counter used as downcounter|
-|:::|//This bit is readonly in center-aligned or encoder mode//||
-|OPM|0|Counter is **not** stopped at update event|
-|:::|1|Counter stops at the next update event|
-|CEN|0|Counter disabled|
-|:::|1|Counter enabled|
-=== CR2 ===
-\\ {{timer_reg_cr2.svg}} \\ \\
-|< 100% 5em 5em >|
-|MMS|000|**Reset**|
-|:::|001|**Enable**|
-|:::|010|**Update**|
-|:::|011|**Compare Pulse**|
-|:::|100|**Compare** OC1REF signal is used as TRGO|
-|:::|101|**Compare** OC2REF signal is used as TRGO|
-|:::|110|**Compare** OC3REF signal is used as TRGO|
-|:::|111|**Compare** OC4REF signal is used as TRGO|
-|CCDS|0|CCx DMA request sent when CCx event occurs|
-|::: |1|CCx DMA request sent when update event occurs|
-=== PSC ===
-\\ {{timer_reg_psc.svg}} \\ \\
-=== ARR ===
-\\ {{timer_reg_arr.svg}} \\ \\
-=== DIER ===
-\\ {{timer_reg_dier.svg}} \\ \\
-|< 100% 5em 5em >|
-|TDE|0|Trigger DMA request disabled|
-|:::|1|Trigger DMA request enabled|
-|CCxDE|0|CCx DMA request disabled|
-|:::  |1|CCx DMA request enabled|
-|UDE|0|Update DMA request disabled|
-|:::|1|Update DMA request enabled|
-|TIE|0|Trigger interrupt disabled|
-|:::|1|Trigger interrupt enabled|
-|CCxIE|0|CCx interrupt disabled|
-|:::  |1|CCx interrupt enabled|
-|UIE|0|Update interrupt disabled|
-|:::|1|Update interrupt enabled|
-=== CCMR1/2 ===
-|< 100% 5em 5em >|
-|CCxS|00|CCx channel is configured as output|
-|::: |01|CCx channel is configured as input, ICx is mapped directly|
-|::: |10|CCx channel is configured as input, ICx is mapped crossed|
-|::: |11|CCx channel is configured as input, ICx is mapped on TRC|
-|:::|//CCxS bits are only writeable when the channel is off (CCxE = 0, CCER)//||
-== Input Configuration ==
-\\ {{timer_reg_ccmr2.svg}} {{timer_reg_ccmr1.svg}} \\ \\
-== Output Configuration ==
-\\ {{timer_reg_ccmr2.svg}} {{timer_reg_ccmr1.svg}} \\ \\
-|< 100% 5em 5em >|
-|OCxM|000|**Frozen** Compairson of CNT and CCRx has no effect on OCxREF|
-|::: |001|**Active** OCxREF high if CNT equals CCRx|
-|::: |010|**Inactive** OCxREF low if CNT equals CCRx|
-|::: |011|**Toggle** OCxREF toggles if CNT equals CCRx|
-|::: |100|**Force Inactive** OCxREF forced low|
-|::: |101|**Forced Active** OCxREF forced high|
-|::: |110|**PWM 1** OCxREF high if CNT < CCRx|
-|::: |111|**PWM 2** OCxREF low if CNT > CCRx|
-=== SMCR - Slave Mode Control Register ===
-\\ {{timer_reg_smcr.svg}} \\ \\
-== ETP - External Trigger Polarity ==
-|< 100% 5em >|
-|0|ETR is **not** inverted, active at high level or rising edge|
-|1|ETR is inverted, active at low level or falling edge|
-== ECE - External Clock Enable ==
-|< 100% 5em >|
-|0|External clock mode 2 disabled|
-|1|External clock mode 2 enabled. Clock enabled by any active edge on ETRF|
-=== CCER ===
-\\ {{timer_reg_ccer.svg}} \\ \\
-=== EGR ===
-\\ {{timer_reg_egr.svg}} \\ \\
-=== SR ===
-\\ {{timer_reg_sr.svg}} \\ \\
-==== Data Registers ====
-=== CNT ===
-\\ {{timer_reg_cnt.svg}} \\ \\
-=== CCRx ===
-\\ {{timer_reg_ccrx.svg}} \\ \\
-===== Legend =====
-\\ {{legende.svg}} \\ \\