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stm32:peripherals:timer_compare [2022/12/28 07:59] – ruanstm32:peripherals:timer_compare [2022/12/28 08:00] (current) – ruan
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 ===== Configuration Registers ===== ===== Configuration Registers =====
  
-==== CCMR1/2 - Capture/compare mode register 1/2 ====+==== TIMx_CCMR1/2 - Capture/compare mode register 1/2 ====
  
 \\ {{timer_reg_ccmr1.svg}} {{timer_reg_ccmr2.svg}} \\ \\ \\ {{timer_reg_ccmr1.svg}} {{timer_reg_ccmr2.svg}} \\ \\
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 |::: |  |//*Note: CCxS bits are writable only when the channel is OFF (CCxE = ‘0’ in TIMx_CCER).//| |::: |  |//*Note: CCxS bits are writable only when the channel is OFF (CCxE = ‘0’ in TIMx_CCER).//|
  
-==== DIER - DMA / Interrupt enable register ====+==== TIMx_DIER - DMA / Interrupt enable register ====
  
 \\ {{timer_reg_dier.svg}} \\ \\ \\ {{timer_reg_dier.svg}} \\ \\
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 |:::  |1|CCx interrupt enabled| |:::  |1|CCx interrupt enabled|
  
-==== CCER - Capture/compare enable register ====+==== TIMx_CCER - Capture/compare enable register ====
  
 \\ {{timer_reg_ccer.svg}} \\ \\ \\ {{timer_reg_ccer.svg}} \\ \\
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 |::: |1|Capture/compare output x enabled| |::: |1|Capture/compare output x enabled|
  
-==== CCRx - Capture/compare enable register ====+==== TIMx_CCRx - Capture/compare enable register ====
  
 \\ {{timer_reg_ccrx.svg}} \\ \\ \\ {{timer_reg_ccrx.svg}} \\ \\
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 |CCRx|15:0|Capture/Compare value| |CCRx|15:0|Capture/Compare value|
  
-==== BDTR - Break and dead-time register ====+==== TIMx_BDTR - Break and dead-time register ====
  
 \\ {{timer_reg_bdtr.svg}} \\ \\ \\ {{timer_reg_bdtr.svg}} \\ \\
  • stm32/peripherals/timer_compare.1672214377.txt.gz
  • Last modified: 2022/12/28 07:59
  • by ruan