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stm32:peripherals:timer_compare [2021/10/08 08:34] – frttstm32:peripherals:timer_compare [2022/12/28 08:00] (current) – ruan
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 \\ {{timer_output.svg}} \\ \\ \\ {{timer_output.svg}} \\ \\
- 
-===== Programming Example ===== 
- 
-The code snippet bellow shows how to configure and use a GPIO pin as input. 
- 
-<code c> 
-#include "reg_stm32f4xx.h" 
- 
-RCC->AHBENR[0] |= (0x1 << 0u);          /* Enable GPIOA clock */ 
-RCC->APBENR[0] |= (0x1 << 0u);          /* Enable TIM2 clock */ 
- 
-/* configure output */ 
-GPIOA->MODER |= (0x2 << 0u);          /* Set pin 0 to Alternate Function */ 
-GPIOA->AFR[0] |= (0x1 << 0u);         /* Set pin 0 to AF1 (TIM2) */ 
-  
-/* configure basic timer */ 
-TIM2->PSC = 84000u - 1u;              /* Counting with f = 84MHz / 84000 = 1MHz */ 
-TIM2->ARR = 512u;                     /* Count to 512 */ 
- 
-/* configure timer output */ 
-TIM2->CCMR1 |= (0x6 << 4u);           /* Enable PWM mode 1 on channel 1 */ 
-TIM2->CCER |= (0x1 << 0u);            /* Enable output on channel 1 */ 
-  
-TIM2->CR1 |= (0x1 << 0u);             /* Start timer */ 
-</code> 
-\\ 
- 
-> {{logo_hal.svg?72px |}} **Hardware Abstraction Layer** 
-> [[https://ennis.zhaw.ch/hal/structreg__tim__t.html | Register Types]] 
-> [[https://ennis.zhaw.ch/hal/hal__timer_8h.html | InES Timer HAL Interface]] 
-\\ 
  
 ===== Configuration Registers ===== ===== Configuration Registers =====
  
-==== CCMR1/2 ==== +==== TIMx_CCMR1/2 - Capture/compare mode register 1/2 ====
- +
-Capture/compare mode register 1/2+
  
 \\ {{timer_reg_ccmr1.svg}} {{timer_reg_ccmr2.svg}} \\ \\ \\ {{timer_reg_ccmr1.svg}} {{timer_reg_ccmr2.svg}} \\ \\
 +
 +**Output compare mode**
  
 |< 100% 5em 5em >| |< 100% 5em 5em >|
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 |::: |110|PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).| |::: |110|PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).|
 |::: |111|PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.| |::: |111|PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.|
 +
 +**Input compare mode**
 +
 +|< 100% 5em 5em >|
 +|ICxF|0000|No filter, f<sub>DTS</sub> (reset state)|1000|f<sub>sampling</sub> => f<sub>DTS</sub> / 8, N=6|
 +|:::|0001|f<sub>sampling</sub> => f<sub>CKINT</sub>, N=2|1001|f<sub>sampling</sub> => f<sub>DTS</sub> / 8, N=8|
 +|:::|0010|f<sub>sampling</sub> => f<sub>CKINT</sub>, N=4|1010|f<sub>sampling</sub> => f<sub>DTS</sub> / 16, N=5|
 +|:::|0011|f<sub>sampling</sub> => f<sub>CKINT</sub>, N=8|1011|f<sub>sampling</sub> => f<sub>DTS</sub> / 16, N=6|
 +|:::|0100|f<sub>sampling</sub> => f<sub>DTS</sub> / 2, N=6|1100|f<sub>sampling</sub> => f<sub>DTS</sub> / 16, N=8|
 +|:::|0101|f<sub>sampling</sub> => f<sub>DTS</sub> / 2, N=8|1101|f<sub>sampling</sub> => f<sub>DTS</sub> / 32, N=5|
 +|:::|0110|f<sub>sampling</sub> => f<sub>DTS</sub> / 4, N=6|1110|f<sub>sampling</sub> => f<sub>DTS</sub> / 32, N=6|
 +|:::|0111|f<sub>sampling</sub> => f<sub>DTS</sub> / 4, N=8|1111|f<sub>sampling</sub> => f<sub>DTS</sub> / 32, N=8|
 +|ICxPSC|00|no prescaler, capture is done each time an edge is detected on the capture input (reset state)|
 +|:::  |01| capture is done once every 2 events|
 +|:::  |10| capture is done once every 4 events|
 +|:::  |11| capture is done once every 8 events|
 +
 +**Select mode**
 +
 |CCxS|00|CCx channel is configured as output| |CCxS|00|CCx channel is configured as output|
 |::: |01|CCx channel is configured as input, ICx is mapped on TIx| |::: |01|CCx channel is configured as input, ICx is mapped on TIx|
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 |::: |  |//*Note: CCxS bits are writable only when the channel is OFF (CCxE = ‘0’ in TIMx_CCER).//| |::: |  |//*Note: CCxS bits are writable only when the channel is OFF (CCxE = ‘0’ in TIMx_CCER).//|
  
-==== DIER ==== +==== TIMx_DIER - DMA / Interrupt enable register ====
- +
-DMA / Interrupt enable register+
  
 \\ {{timer_reg_dier.svg}} \\ \\ \\ {{timer_reg_dier.svg}} \\ \\
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 |:::  |1|CCx interrupt enabled| |:::  |1|CCx interrupt enabled|
  
-==== CCER ==== +==== TIMx_CCER - Capture/compare enable register ====
- +
-Capture/compare enable register+
  
 \\ {{timer_reg_ccer.svg}} \\ \\ \\ {{timer_reg_ccer.svg}} \\ \\
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 |::: |1|Capture/compare output x enabled| |::: |1|Capture/compare output x enabled|
  
-==== CCRx ==== +==== TIMx_CCRx - Capture/compare enable register ====
- +
-Capture/compare enable register+
  
 \\ {{timer_reg_ccrx.svg}} \\ \\ \\ {{timer_reg_ccrx.svg}} \\ \\
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 |CCRx|15:0|Capture/Compare value| |CCRx|15:0|Capture/Compare value|
  
-===== Legend =====+==== TIMx_BDTR - Break and dead-time register ====
  
-\\ {{legende.svg}} \\ \\+\\ {{timer_reg_bdtr.svg}} \\ \\ 
 + 
 +|< 100% 5em 5em >| 
 +|MOE|0|OC and OCN outputs are disabled or forced to idle state. (reset state)| 
 +|:::|1| OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register).| 
 + 
 +===== Programming Example ===== 
 + 
 +The code snippet below shows how to configure and use a GPIO pin as input. 
 + 
 +<code c> 
 +#include "reg_stm32f4xx.h" 
 + 
 +RCC->AHBENR[0] |= (0x1 << 0u);          /* Enable GPIOA clock */ 
 +RCC->APBENR[0] |= (0x1 << 0u);          /* Enable TIM2 clock */ 
 + 
 +/* configure output */ 
 +GPIOA->MODER |= (0x2 << 0u);          /* Set pin 0 to Alternate Function */ 
 +GPIOA->AFR[0] |= (0x1 << 0u);         /* Set pin 0 to AF1 (TIM2) */ 
 +  
 +/* configure basic timer */ 
 +TIM2->PSC = 84000u - 1u;              /* Counting with f = 84MHz / 84000 = 1MHz */ 
 +TIM2->ARR = 512u;                     /* Count to 512 */ 
 + 
 +/* configure timer output */ 
 +TIM2->CCMR1 |= (0x6 << 4u);           /* Enable PWM mode 1 on channel 1 */ 
 +TIM2->CCER |= (0x1 << 0u);            /* Enable output on channel 1 */ 
 +  
 +TIM2->CR1 |= (0x1 << 0u);             /* Start timer */ 
 +</code> 
 +\\
  • stm32/peripherals/timer_compare.1633682080.txt.gz
  • Last modified: 2021/10/08 08:34
  • by frtt