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stm32:peripherals:timer_2..5 [2016/01/26 06:36] – [Configuration Registers] feur | stm32:peripherals:timer_2..5 [2016/06/28 07:46] (current) – removed feur | ||
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- | ====== Timer 2..5 ====== | ||
- | The STM32F429ZI offers several general purpouse timers. Timer 2 and 5 are 32 bit timers, while timer 3 and 4 are 16 bit timers. They may be used for measuring time (basic timer), measuring input pulse length (input capturing) or generating waveforms (output compare / PWM). The timers are fully independent and can be synchronized together. | ||
- | |||
- | \\ {{timer_complete.svg}} \\ \\ | ||
- | |||
- | ===== Features ===== | ||
- | |||
- | * 16-bit / 32-bit up, down, up/down auto-reload counter. | ||
- | * Prescaler (16 bit) to adjust counting clock, even during runtime. | ||
- | * 4 independent channels for: | ||
- | * Input capture | ||
- | * Output compare | ||
- | * PWM generation (edge- and center-aligned) | ||
- | * One-pulse output | ||
- | * Synchronization / control through external signals. | ||
- | * Interrupt / DMA generation. | ||
- | |||
- | ===== Functions ===== | ||
- | |||
- | ==== Base Timer ==== | ||
- | |||
- | \\ {{timer_base.svg}} \\ \\ | ||
- | |||
- | == Configuration Registers == | ||
- | |||
- | |< 100% 10em >| | ||
- | |[[# | ||
- | |[[# | ||
- | |[[# | ||
- | |[[# | ||
- | |||
- | == Data Registers == | ||
- | |||
- | |< 100% 10em >| | ||
- | |[[# | ||
- | |||
- | === Upcounting === | ||
- | |||
- | === Downcounting === | ||
- | |||
- | === Up/Down counting === | ||
- | |||
- | ==== Clock Source ==== | ||
- | |||
- | \\ {{timer_clock.svg}} \\ \\ | ||
- | |||
- | ==== Output Compare ==== | ||
- | |||
- | \\ {{timer_output.svg}} \\ \\ | ||
- | |||
- | ===== Registers ===== | ||
- | |||
- | ==== Configuration Registers ==== | ||
- | |||
- | === CR1 === | ||
- | |||
- | \\ {{timer_reg_cr1.svg}} \\ \\ | ||
- | |||
- | === CR2 === | ||
- | |||
- | \\ {{timer_reg_cr2.svg}} \\ \\ | ||
- | |||
- | === PSC === | ||
- | |||
- | \\ {{timer_reg_psc.svg}} \\ \\ | ||
- | |||
- | === ARR === | ||
- | |||
- | \\ {{timer_reg_arr.svg}} \\ \\ | ||
- | |||
- | === DIER === | ||
- | |||
- | \\ {{timer_reg_dier.svg}} \\ \\ | ||
- | |||
- | === CCMR1/2 === | ||
- | |||
- | == Input Configuration == | ||
- | |||
- | \\ {{timer_reg_ccmr1.svg}} \\ \\ | ||
- | |||
- | \\ {{timer_reg_ccmr2.svg}} \\ \\ | ||
- | |||
- | == Output Configuration == | ||
- | \\ {{timer_reg_ccmr1.svg}} \\ \\ | ||
- | |||
- | \\ {{timer_reg_ccmr2.svg}} \\ \\ | ||
- | |||
- | === SMCR === | ||
- | |||
- | \\ {{timer_reg_smcr.svg}} \\ \\ | ||
- | |||
- | === CCER === | ||
- | |||
- | \\ {{timer_reg_ccer.svg}} \\ \\ | ||
- | |||
- | === EGR === | ||
- | |||
- | \\ {{timer_reg_egr.svg}} \\ \\ | ||
- | |||
- | === SR === | ||
- | |||
- | \\ {{timer_reg_sr.svg}} \\ \\ | ||
- | |||
- | ==== Data Registers ==== | ||
- | |||
- | === CNT === | ||
- | |||
- | \\ {{timer_reg_cnt.svg}} \\ \\ | ||
- | |||
- | === CCRx === | ||
- | |||
- | \\ {{timer_reg_ccrx.svg}} \\ \\ | ||
- | |||
- | ===== Legende ===== | ||
- | |||
- | \\ {{legende.svg}} \\ \\ |