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stm32:peripherals:spi [2016/09/21 11:56] – old revision restored (2016/06/07 07:05) feurstm32:peripherals:spi [2022/12/28 08:36] (current) – [SPI_CR1 Configuration register 1] ruan
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   * Slave select either by hardware or software.   * Slave select either by hardware or software.
   * Interrupt, CRC and DMA support.   * Interrupt, CRC and DMA support.
-\\ 
- 
-===== Programming Example ===== 
- 
-The code snippet bellow shows how to configure and use the SPI peripheral. 
- 
-<code c> 
-#include "reg_stm32f4xx.h" 
- 
-RCC->AHBENR[0] |= (0x1 << 0u);       /* Enable GPIOA clock */ 
-RCC->APBENR[1] |= (0x1 << 12u);      /* Enable SPI1 clock */ 
- 
-/* Configure GPIO pin A.4 to A.7 in alternate function mode. */ 
-GPIOA->MODER &= ~(0xff << 8u);       /* Clear existing mode bits 8 to 15. */ 
-GPIOA->MODER |= (0xaa << 8u);        /* Set pin 4..7 to alternate function mode. */ 
- 
-GPIOA->OSPEEDR &= ~(0xff << 8u);     /* Clear existing output speed bits 8 to 15. */ 
-GPIOA->OSPEEDR |= (0xff << 8u);      /* Set pin 4..7 to high speed (100MHz) mode. */ 
- 
-GPIOA->AFR[0] &= ~(0xffff << 16u);   /* Clear existing af bits 16 to 31. */ 
-GPIOA->AFR[0] |= (0x5555 << 16u);    /* Set pin 4..7 to AF5 (SPI1). */ 
- 
-/* Configure SPI1 in slave mode. */ 
-SPI1->CR1 = 0u;                      /* Reset SPI1 configuration. */ 
-SPI1->CR2 = 0u;                      /* Reset SPI1 configuration. */ 
- 
-SPI1->CR1 |= (0x1 << 3u) |           /* Select 11,25MHz as baudrate (45 MHz / 4). */ 
-             (0x1 << 6u);            /* Enable SPI. */ 
- 
-</code> 
-\\ 
- 
-> {{logo_hal.svg?72px |}} **Hardware Abstraction Layer** 
-> [[https://ennis.zhaw.ch/hal/structreg__spi__t.html | Registry Types]] 
-> [[https://ennis.zhaw.ch/hal/hal__spi_8h.html | InES SPI HAL Interface]] 
 \\ \\
  
 ===== Configuration Registers ===== ===== Configuration Registers =====
  
-==== CRx ==== +==== SPI_CR1 - Configuration register 1 ====
- +
-=== CR1 === +
- +
-Configuration register 1 \\+
 (not used in I²S mode) (not used in I²S mode)
  
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 |:::|1|Data frame: 16 bit|| |:::|1|Data frame: 16 bit||
  
-=== CR2 === +==== SPI_CR2 - Configuration register 2 ====
- +
-Configuration register 2+
  
 \\ {{spi_reg_cr2.svg}} \\ \\ \\ {{spi_reg_cr2.svg}} \\ \\
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 |:::|1|TX empty interrupt enabled| |:::|1|TX empty interrupt enabled|
  
-==== CRCPR ==== +==== SPI_CRCPR - CRC polynomial register ====
- +
-CRC polynomial register \\+
 (not used in I²S mode) (not used in I²S mode)
  
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 Contains polynomial used to calculate CRC. Reset value: ''0x0007''. \\ Contains polynomial used to calculate CRC. Reset value: ''0x0007''. \\
  
-==== RXCRCR ==== +==== SPI_RXCRCR - RX CRC register ====
- +
-RX CRC register \\+
 (not used in I²S mode) (not used in I²S mode)
  
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 Contains computed CRC value of received bytes. \\ Contains computed CRC value of received bytes. \\
  
-==== TXCRCR ==== +==== SPI_TXCRCR - TX CRC register ====
- +
-TX CRC register \\+
 (not used in I²S mode) (not used in I²S mode)
  
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 Contains computed CRC value of transmitted bytes. \\ Contains computed CRC value of transmitted bytes. \\
  
-==== I2SCFGR ==== +==== SPI_I2SCFGR - I²S configuration register ====
- +
-I²S configuration register \\+
 (not used in SPI mode) (not used in SPI mode)
  
 \\ {{spi_reg_i2scfgr.svg}} \\ \\ \\ {{spi_reg_i2scfgr.svg}} \\ \\
  
-==== I2SPR ==== +==== SPI_I2SPR - I²S prescaler register ====
- +
-I²S prescaler register \\+
 (not used in SPI mode) (not used in SPI mode)
  
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 ===== Data Register ===== ===== Data Register =====
  
-==== DR ==== +==== SPI_DR - Data register ====
- +
-Data register+
  
 \\ {{spi_reg_dr.svg}} \\ \\ \\ {{spi_reg_dr.svg}} \\ \\
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 \\ \\
  
-===== Legend =====+===== Programming Example ===== 
 + 
 +The code snippet bellow shows how to configure and use the SPI peripheral. 
 + 
 +<code c> 
 +#include "reg_stm32f4xx.h" 
 + 
 +RCC->AHBENR[0] |= (0x1 << 0u);       /* Enable GPIOA clock */ 
 +RCC->APBENR[1] |= (0x1 << 12u);      /* Enable SPI1 clock */ 
 + 
 +/* Configure GPIO pin A.4 to A.7 in alternate function mode. */ 
 +GPIOA->MODER &= ~(0xff << 8u);       /* Clear existing mode bits 8 to 15. */ 
 +GPIOA->MODER |= (0xaa << 8u);        /* Set pin 4..7 to alternate function mode. */ 
 + 
 +GPIOA->OSPEEDR &= ~(0xff << 8u);     /* Clear existing output speed bits 8 to 15. */ 
 +GPIOA->OSPEEDR |= (0xff << 8u);      /* Set pin 4..7 to high speed (100MHz) mode. */ 
 + 
 +GPIOA->AFR[0] &= ~(0xffff << 16u);   /* Clear existing af bits 16 to 31. */ 
 +GPIOA->AFR[0] |= (0x5555 << 16u);    /* Set pin 4..7 to AF5 (SPI1). */ 
 + 
 +/* Configure SPI1 in slave mode. */ 
 +SPI1->CR1 = 0u;                      /* Reset SPI1 configuration. */ 
 +SPI1->CR2 = 0u;                      /* Reset SPI1 configuration. */ 
 + 
 +SPI1->CR1 |= (0x1 << 3u) |           /* Select 11,25MHz as baudrate (45 MHz / 4). */ 
 +             (0x1 << 6u);            /* Enable SPI. */ 
 + 
 +</code> 
 +\\
  
-\\ {{legende.svg}} \\ \\ 
  • stm32/peripherals/spi.1474458999.txt.gz
  • Last modified: 2016/09/21 11:56
  • by feur