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stm32:peripherals:spi [2016/02/26 19:05] – [Programming Example] feurstm32:peripherals:spi [2022/12/28 08:36] (current) – [SPI_CR1 Configuration register 1] ruan
Line 15: Line 15:
   * Slave select either by hardware or software.   * Slave select either by hardware or software.
   * Interrupt, CRC and DMA support.   * Interrupt, CRC and DMA support.
-\\ 
- 
-===== Programming Example ===== 
- 
-The code snippet bellow shows how to configure and use the SPI peripheral. 
- 
-<code c> 
-#include "reg_stm32f4xx.h" 
- 
-RCC->AHBENR[0] |= (0x1 << 0u);       /* Enable GPIOA clock */ 
-RCC->APBENR[1] |= (0x1 << 12u);      /* Enable SPI1 clock */ 
- 
-/* Configure GPIO pin A.4 to A.7 in alternate function mode. */ 
-GPIOA->MODER &= ~(0xff << 8u);       /* Clear existing mode bits 8 to 15. */ 
-GPIOA->MODER |= (0xaa << 8u);        /* Set pin 4..7 to alternate function mode. */ 
- 
-GPIOA->OSPEEDR &= ~(0xff << 8u);     /* Clear existing output speed bits 8 to 15. */ 
-GPIOA->OSPEEDR |= (0xff << 8u);      /* Set pin 4..7 to high speed (100MHz) mode. */ 
- 
-GPIOA->AFR[0] &= ~(0xffff << 0u);    /* Clear existing output speed bits 8 to 15. */ 
-GPIOA->AFR[0] |= (0x5555 << 8u);     /* Set pin 4..7 to AF5 (SPI1). */ 
- 
-/* Configure SPI1 in slave mode. */ 
-SPI1->CR1 = 0u;                      /* Reset SPI1 configuration. */ 
-SPI1->CR2 = 0u;                      /* Reset SPI1 configuration. */ 
- 
-SPI1->CR1 |= (0x1 << 3u) |           /* Select 11,25MHz as baudrate (45 MHz / 4). */ 
-             (0x1 << 6u) |           /* Enable SPI. */ 
- 
-</code> 
 \\ \\
  
 ===== Configuration Registers ===== ===== Configuration Registers =====
  
-==== CRx ==== +==== SPI_CR1 - Configuration register 1 ====
- +
-Configuration register 1 \\+
 (not used in I²S mode) (not used in I²S mode)
  
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 |MSTR|0|Slave mode (reset state)|| |MSTR|0|Slave mode (reset state)||
 |:::|1|Master mode|| |:::|1|Master mode||
-|BR|000|f<sub>PCLK</sub> / 2 (reset state)|100|f<sub>PCLK</sub> / 32| +|BR|000|BR => f<sub>PCLK2</sub> / 2 (reset state)|100|BR => f<sub>PCLK2</sub> / 32| 
-|:::|001|f<sub>PCLK</sub> / 4|101|f<sub>PCLK</sub> / 64| +|:::|001|BR => f<sub>PCLK2</sub> / 4|101|BR => f<sub>PCLK2</sub> / 64| 
-|:::|010|f<sub>PCLK</sub> / 8|110|f<sub>PCLK</sub> / 128| +|:::|010|BR => f<sub>PCLK2</sub> / 8|110|BR => f<sub>PCLK2</sub> / 128| 
-|:::|011|f<sub>PCLK</sub> / 16|111|f<sub>PCLK</sub> / 256|+|:::|011|BR => f<sub>PCLK2</sub> / 16|111|BR => f<sub>PCLK2</sub> / 256|
 |SPE|0|SPI disabled (reset state)|| |SPE|0|SPI disabled (reset state)||
 |:::|1|SPI enabled|| |:::|1|SPI enabled||
Line 72: Line 40:
 |:::|1|Data frame: 16 bit|| |:::|1|Data frame: 16 bit||
  
-Configuration register 2+==== SPI_CR2 - Configuration register 2 ====
  
 \\ {{spi_reg_cr2.svg}} \\ \\ \\ {{spi_reg_cr2.svg}} \\ \\
Line 88: Line 56:
 |:::|1|TX empty interrupt enabled| |:::|1|TX empty interrupt enabled|
  
-==== CRCPR ==== +==== SPI_CRCPR - CRC polynomial register ====
- +
-CRC polynomial register \\+
 (not used in I²S mode) (not used in I²S mode)
  
Line 97: Line 63:
 Contains polynomial used to calculate CRC. Reset value: ''0x0007''. \\ Contains polynomial used to calculate CRC. Reset value: ''0x0007''. \\
  
-==== RXCRCR ==== +==== SPI_RXCRCR - RX CRC register ====
- +
-RX CRC register \\+
 (not used in I²S mode) (not used in I²S mode)
  
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 Contains computed CRC value of received bytes. \\ Contains computed CRC value of received bytes. \\
  
-==== TXCRCR ==== +==== SPI_TXCRCR - TX CRC register ====
- +
-TX CRC register \\+
 (not used in I²S mode) (not used in I²S mode)
  
Line 115: Line 77:
 Contains computed CRC value of transmitted bytes. \\ Contains computed CRC value of transmitted bytes. \\
  
-==== I2SCFGR ==== +==== SPI_I2SCFGR - I²S configuration register ====
- +
-I²S configuration register \\+
 (not used in SPI mode) (not used in SPI mode)
  
 \\ {{spi_reg_i2scfgr.svg}} \\ \\ \\ {{spi_reg_i2scfgr.svg}} \\ \\
  
-==== I2SPR ==== +==== SPI_I2SPR - I²S prescaler register ====
- +
-I²S prescaler register \\+
 (not used in SPI mode) (not used in SPI mode)
  
Line 131: Line 89:
 ===== Data Register ===== ===== Data Register =====
  
-==== DR ==== +==== SPI_DR - Data register ====
- +
-Data register+
  
 \\ {{spi_reg_dr.svg}} \\ \\ \\ {{spi_reg_dr.svg}} \\ \\
  
 Data received or to be transmitted. Split into 2 buffers: Data received or to be transmitted. Split into 2 buffers:
-  * Writing to DR writes to the Transmit Buffer. +  * Writing to DR writes to TX Buffer. 
-  * Reading from DR reads from Read Buffer. +  * Reading from DR reads from RX Buffer. 
 \\ \\
  
-===== Legend =====+===== Programming Example ===== 
 + 
 +The code snippet bellow shows how to configure and use the SPI peripheral. 
 + 
 +<code c> 
 +#include "reg_stm32f4xx.h" 
 + 
 +RCC->AHBENR[0] |= (0x1 << 0u);       /* Enable GPIOA clock */ 
 +RCC->APBENR[1] |= (0x1 << 12u);      /* Enable SPI1 clock */ 
 + 
 +/* Configure GPIO pin A.4 to A.7 in alternate function mode. */ 
 +GPIOA->MODER &= ~(0xff << 8u);       /* Clear existing mode bits 8 to 15. */ 
 +GPIOA->MODER |= (0xaa << 8u);        /* Set pin 4..7 to alternate function mode. */ 
 + 
 +GPIOA->OSPEEDR &= ~(0xff << 8u);     /* Clear existing output speed bits 8 to 15. */ 
 +GPIOA->OSPEEDR |= (0xff << 8u);      /* Set pin 4..7 to high speed (100MHz) mode. */ 
 + 
 +GPIOA->AFR[0] &= ~(0xffff << 16u);   /* Clear existing af bits 16 to 31. */ 
 +GPIOA->AFR[0] |= (0x5555 << 16u);    /* Set pin 4..7 to AF5 (SPI1). */ 
 + 
 +/* Configure SPI1 in slave mode. */ 
 +SPI1->CR1 = 0u;                      /* Reset SPI1 configuration. */ 
 +SPI1->CR2 = 0u;                      /* Reset SPI1 configuration. */ 
 + 
 +SPI1->CR1 |= (0x1 << 3u) |           /* Select 11,25MHz as baudrate (45 MHz / 4). */ 
 +             (0x1 << 6u);            /* Enable SPI. */ 
 + 
 +</code> 
 +\\
  
-\\ {{legende.svg}} \\ \\ 
  • stm32/peripherals/spi.1456513545.txt.gz
  • Last modified: 2016/02/26 19:05
  • by feur