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| Both sides previous revision Previous revision Next revision | Previous revision | ||
| stm32:peripherals:rtc_wakeup [2021/09/03 08:52] – frtt: Initially Add BDCR register frtt | stm32:peripherals:rtc_wakeup [2022/12/27 18:42] (current) – ruan | ||
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| Line 56: | Line 56: | ||
| ===== Configuration Registers ===== | ===== Configuration Registers ===== | ||
| - | ==== RTC_CR ==== | + | ==== RTC_CR |
| - | + | ||
| - | Configuration register | + | |
| \\ {{rtc_reg_cr.svg}} \\ \\ | \\ {{rtc_reg_cr.svg}} \\ \\ | ||
| Line 72: | Line 70: | ||
| |:::|1|Wake up timer interrupt enabled|| | |:::|1|Wake up timer interrupt enabled|| | ||
| - | ==== RTC_WUTR ==== | + | ==== RTC_WUTR |
| - | + | ||
| - | Wakeup timer register | + | |
| \\ {{rtc_reg_wutr.svg}} \\ \\ | \\ {{rtc_reg_wutr.svg}} \\ \\ | ||
| Line 81: | Line 77: | ||
| ===== Status Registers ===== | ===== Status Registers ===== | ||
| - | ==== RTC_ISR | + | ==== RTC_ISR |
| - | + | ||
| - | Initialization and status register | + | |
| \\ {{rtc_reg_isr.svg}} \\ \\ | \\ {{rtc_reg_isr.svg}} \\ \\ | ||
| Line 95: | Line 89: | ||
| ===== Back domain control register ===== | ===== Back domain control register ===== | ||
| - | ==== RCC_BDCR | + | ==== RCC_BDCR |
| - | Back domain control register | + | |
| \\ {{rcc_reg_bdcr.svg}} \\ \\ | \\ {{rcc_reg_bdcr.svg}} \\ \\ | ||