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stm32:peripherals:rtc_wakeup [2017/10/24 10:41] – [Setup wakeup timer] kjazstm32:peripherals:rtc_wakeup [2022/12/27 18:42] (current) ruan
Line 40: Line 40:
   * Program reload value in ''RTC->WUTR''.   * Program reload value in ''RTC->WUTR''.
   * Enable wakeup interrupt in ''RTC->CR''.   * Enable wakeup interrupt in ''RTC->CR''.
-  * Clear any pending wakeup interrupt flag in ''RTC->ISR''. 
  
 To use the wakeup interrupt, you need to configure the EXTI channel \\ To use the wakeup interrupt, you need to configure the EXTI channel \\
 and enable it in the NVIC: and enable it in the NVIC:
 +  * Clear any pending wakeup interrupt flag in ''RTC->ISR''.
   * Configure the dedicated [[exti|EXTI interrupt]] channel for the RTC. \\ I.e. select edge and enable.   * Configure the dedicated [[exti|EXTI interrupt]] channel for the RTC. \\ I.e. select edge and enable.
   * Enable the RTC wakeup interrupt in the [[nvic|NVIC]].   * Enable the RTC wakeup interrupt in the [[nvic|NVIC]].
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 ===== Configuration Registers ===== ===== Configuration Registers =====
  
-==== RTC_CR ==== +==== RTC_CR - Configuration register ====
- +
-Configuration register+
  
 \\ {{rtc_reg_cr.svg}} \\ \\ \\ {{rtc_reg_cr.svg}} \\ \\
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 |:::|1|Wake up timer interrupt enabled|| |:::|1|Wake up timer interrupt enabled||
  
-==== RTC_WUTR ==== +==== RTC_WUTR - Wakeup timer register ====
- +
-Wakeup timer register+
  
 \\ {{rtc_reg_wutr.svg}} \\ \\ \\ {{rtc_reg_wutr.svg}} \\ \\
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 ===== Status Registers ===== ===== Status Registers =====
  
-==== RTC_ISR ==== +==== RTC_ISR Initialization and status register ====
- +
-Initialization and status register+
  
 \\ {{rtc_reg_isr.svg}} \\ \\ \\ {{rtc_reg_isr.svg}} \\ \\
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 |WUTWF*|0|Wake up timer configuration not allowed| |WUTWF*|0|Wake up timer configuration not allowed|
 |:::|1|Wake up timer configuration allowed| |:::|1|Wake up timer configuration allowed|
 +|WUTF||Wake up timer flag is set by hardware when wakeup counter reaches 0 and cleared by software by writing 0.||
 * This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware. * This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware.
 +
 +===== Back domain control register =====
 +
 +==== RCC_BDCR - Back domain control register ====
 +
 +\\ {{rcc_reg_bdcr.svg}} \\ \\ 
 +
 +|< 100% 5em 5em >|
 +|RTCEN*|0|RTC clock disabled|
 +|:::|1|RTC clock enabled|
 +|RTCSEL|00|No clock|
 +|:::|01|LSE oscillator clock used as the RTC clock|
 +|:::|10|LSI oscillator clock used as the RTC clock|
 +|:::|11|HSE oscillator clock divided by a programmable prescaler(selection Through RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC clock|
 +
  • stm32/peripherals/rtc_wakeup.1508841673.txt.gz
  • Last modified: 2017/10/24 10:41
  • by kjaz