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| Both sides previous revision Previous revision Next revision | Previous revision | ||
| stm32:peripherals:rcc_peripherals [2022/12/27 19:18] – [RCC_xxxENR - Peripheral clock enable register] ruan | stm32:peripherals:rcc_peripherals [2022/12/27 19:24] (current) – [RCC: Enable/disable clocks for peripherals and reset peripherals] ruan | ||
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| - | ====== RCC: Enable/ | + | ====== RCC Enable/ |
| The peripherals can be controlled by the following 3 register sets: | The peripherals can be controlled by the following 3 register sets: | ||
| - | * The [[#xxxENR]] registers | + | * The [[#RCC_xxxxENR - Peripheral clock enable registers]] enable or disable the clocks for the peripherals. |
| - | * The [[#xxxLPENR]] registers | + | * The [[#RCC_xxxxLPENR Low power clock enable registers]] enable or disable the clocks for the peripherals in sleep mode. |
| - | * The [[#xxxRSTR]] registers | + | * The [[#RCC_xxxxRSTR - Peripheral reset registers]] can reset a peripheral. |
| \\ {{clock_peripherals.svg}} \\ \\ | \\ {{clock_peripherals.svg}} \\ \\ | ||
| Line 35: | Line 35: | ||
| \\ | \\ | ||
| - | ==== RCC_xxxxENR - Peripheral clock enable | + | ==== RCC_xxxxENR - Peripheral clock enable |
| \\ \\ | \\ \\ | ||
| Line 43: | Line 43: | ||
| |zEN|1|Peripheral clock enabled| | |zEN|1|Peripheral clock enabled| | ||
| - | ==== RCC_xxxLPENR | + | ==== RCC_xxxxLPENR |
| \\ \\ | \\ \\ | ||
| Line 51: | Line 51: | ||
| |zLPEN|1|Peripheral clock enabled during sleep mode| | |zLPEN|1|Peripheral clock enabled during sleep mode| | ||
| - | ==== RCC_xxxRSTR | + | ==== RCC_xxxxRSTR |
| \\ \\ | \\ \\ | ||