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stm32:peripherals:rcc_clock [2016/10/14 07:02] – [CFGR] feurstm32:peripherals:rcc_clock [2022/12/27 19:27] (current) – [Setup System Clocks] ruan
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-====== Setup System Clocks ======+====== RCC Setup System Clocks ======
  
 To setup the system clocks you have to: To setup the system clocks you have to:
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 uint32_t reg; uint32_t reg;
  
-RCC->CFGR |= (0x8 << 4u);             /* HPRE: HCLK => 168 MHz / 2 => 84 MHz */ +RCC->CFGR |= (0x8 << 4u);             /* HPRE:  HCLK  => 168 MHz / 2 => 84 MHz */ 
-RCC->CFGR |= (0x4 << 10u);            /* PPRE1: PCLK1 => 84 MHz / 2 => 42 MHz */ +RCC->CFGR |= (0x4 << 10u);            /* PPRE1: PCLK1 =>  84 MHz / 2 => 42 MHz */ 
-RCC->CFGR |= (0x0 << 13u);            /* PPRE2: PCLK2 => 84 MHz / 1 => 84 MHz  +RCC->CFGR |= (0x0 << 13u);            /* PPRE2: PCLK2 =>  84 MHz / 2 => 42 MHz  
-                                                TCLK => 84 MHz • 1 => 84MHz */+                                                TCLK  =>  42 MHz • 2 => 84MHz */
  
 RCC->CFGR |= (0x2 << 0u);             /* Choose PLLCLK as input. */ RCC->CFGR |= (0x2 << 0u);             /* Choose PLLCLK as input. */
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 ===== Configuration Registers ===== ===== Configuration Registers =====
  
-==== CR ==== +==== CR - Control register ====
- +
-Control register+
  
 \\ {{clock_reg_cr.svg}} \\ \\ \\ {{clock_reg_cr.svg}} \\ \\
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 |:::|1|X ready| |:::|1|X ready|
  
-==== PLLCFGR ====+==== CSR - Control and status register ====
  
-PLL configuration register+\\ {{clock_reg_csr.svg}} \\ \\ 
 + 
 +|< 100% 5em 5em >| 
 +|LSION|0|Internal low speed clock enabled| 
 +|:::|1|Internal low speed clock disabled (reset state)| 
 +|LSIRDY|0|Internal low speed clock **not** ready| 
 +|:::|1|Internal low speed clock ready (reset state)| 
 + 
 +==== PLLCFGR - PLL configuration register ====
  
 \\ {{clock_reg_pllcfgr.svg}} \\ \\ \\ {{clock_reg_pllcfgr.svg}} \\ \\
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 * Please refer to reference manual (p.162ff) for detailed explanation of register values. \\ \\ * Please refer to reference manual (p.162ff) for detailed explanation of register values. \\ \\
  
-==== CFGR ==== +==== CFGR - Configuration register ====
- +
-Configuration register+
  
 \\ {{clock_reg_cfgr.svg}} \\ \\ \\ {{clock_reg_cfgr.svg}} \\ \\
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 |:::|01|Enable HSE as SYSCLK|| |:::|01|Enable HSE as SYSCLK||
 |:::|10|Enable PLL as SYSCLK|| |:::|10|Enable PLL as SYSCLK||
-|SWS|00|HSI used as SYSCLK (reset state)||+|SWS|00|HSI used as SYSCLK||
 |:::|01|HSE used as SYSCLK|| |:::|01|HSE used as SYSCLK||
 |:::|10|PLL used as SYSCLK|| |:::|10|PLL used as SYSCLK||
  • stm32/peripherals/rcc_clock.1476428562.txt.gz
  • Last modified: 2016/10/14 07:02
  • by feur