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stm32:peripherals:rcc_clock [2016/02/29 13:14] – feurstm32:peripherals:rcc_clock [2022/12/27 19:27] (current) – [Setup System Clocks] ruan
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-====== Setup System Clocks ======+====== RCC Setup System Clocks ======
  
 To setup the system clocks you have to: To setup the system clocks you have to:
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   * Configure the [[#clock_ratios|clock ratios]].   * Configure the [[#clock_ratios|clock ratios]].
 \\ \\
 +
 +==== Available Oscillators ====
 +
 +|< 100% 5em 5em >|
 +^ ^f<sub>typical</sub>^^
 +|LSI|32 kHz|Low speed internal oscillator|
 +|LSE|32 kHz|Low speed external oscillator|
 +|HSI|16 MHz|High speed internal oscillator|
 +|HSE|8 MHz|High speed external oscillator|
 +
 +==== Available Clocks ====
 +
 +|< 100% 5em 5em >|
 +^ ^f<sub>typical</sub>^^
 +|PLLCLK|var.|PLL clock, used to generate all other clocks|
 +|PLL48CLK|48 MHz|PLL48 clock, used for USB or SDIO|
 +|RTCCLK|var.|RTC clock, used by real time clock|
 +|SYSCLK|168 MHz|System clock, used by CPU|
 +|HCLK|84 MHz|AHB clock, used for AHB peripherals|
 +|PCLK1|42 MHz|APB1 clock, used for APB1 peripherals|
 +|PCLK2|84 MHz|APB2 clock, used for APB2 peripherals|
 +|TCLK|84 MHz|Timer clock, used for the timers|
  
 ===== Clock Source ===== ===== Clock Source =====
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   * Set xxxON bit of desired oscillator.   * Set xxxON bit of desired oscillator.
   * Wait until xxxRDY flag is set.   * Wait until xxxRDY flag is set.
 +\\
  
 <code c> <code c>
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   * Choose PLLN and PLLP values, so that you reach the desired system clock frequency.   * Choose PLLN and PLLP values, so that you reach the desired system clock frequency.
   * If USB is used, choose PLLQ value, so that f<sub>PLL48CLK</sub> is 48 MHz.   * If USB is used, choose PLLQ value, so that f<sub>PLL48CLK</sub> is 48 MHz.
 +\\
  
 <code c> <code c>
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 uint32_t reg; uint32_t reg;
 RCC->PLLCFGR |= (0x4 << 0u);          /* PLLM: input => 8 MHz / 4 => 2 MHz */ RCC->PLLCFGR |= (0x4 << 0u);          /* PLLM: input => 8 MHz / 4 => 2 MHz */
-RCC->PLLCFGR |= (168u << 6u);         /* PLLN: VCO => 2 MHz * 168 => 336 MHz */ +RCC->PLLCFGR |= (168u << 6u);         /* PLLN: VCO => 2 MHz • 168 => 336 MHz */ 
-RCC->PLLCFGR |= (0x0 << 16u);         /* PLLP: SYSCLK => 336 MHz / 2 => 168 MHz */+RCC->PLLCFGR |= (0x0 << 16u);         /* PLLP: PLLCLK => 336 MHz / 2 => 168 MHz */
 RCC->PLLCFGR |= (7u << 24u);          /* PLLQ: PLL48CLK => 336 MHz / 7 => 48 MHz */ RCC->PLLCFGR |= (7u << 24u);          /* PLLQ: PLL48CLK => 336 MHz / 7 => 48 MHz */
 RCC->PLLCFGR |= (0x1 << 22u);         /* Choose HSE as PLL input clock. */ RCC->PLLCFGR |= (0x1 << 22u);         /* Choose HSE as PLL input clock. */
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   * Choose HPRE, maximum allowed clock on AHB is 168 MHz.   * Choose HPRE, maximum allowed clock on AHB is 168 MHz.
   * Choose PPRE1, maximum allowed clock on APB1 is 42 MHz.   * Choose PPRE1, maximum allowed clock on APB1 is 42 MHz.
-  * Choose PPRE2, maximum allowed clock on APB2 is 168 MHz.+  * Choose PPRE2, maximum allowed clock on APB2 is 84 MHz.
   * Select input source.   * Select input source.
 +\\
  
 <code c> <code c>
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 uint32_t reg; uint32_t reg;
  
-RCC->CFGR |= (0x8 << 4u);             /* HPRE: HCLK => 168 MHz / 2 => 84 MHz */ +RCC->CFGR |= (0x8 << 4u);             /* HPRE:  HCLK  => 168 MHz / 2 => 84 MHz */ 
-RCC->CFGR |= (0x4 << 10u);            /* PPRE1: PCLK1 => 84 MHz / 2 => 42 MHz */ +RCC->CFGR |= (0x4 << 10u);            /* PPRE1: PCLK1 =>  84 MHz / 2 => 42 MHz */ 
-RCC->CFGR |= (0x0 << 13u);            /* PPRE2: PCLK2 => 84 MHz / 1 => 84 MHz  +RCC->CFGR |= (0x0 << 13u);            /* PPRE2: PCLK2 =>  84 MHz / 2 => 42 MHz  
-                                                TCLK => 84 MHz * 1 => 84MHz */+                                                TCLK  =>  42 MHz • 2 => 84MHz */
  
 RCC->CFGR |= (0x2 << 0u);             /* Choose PLLCLK as input. */ RCC->CFGR |= (0x2 << 0u);             /* Choose PLLCLK as input. */
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 } }
 </code> </code>
 +\\
  
 ===== Configuration Registers ===== ===== Configuration Registers =====
  
-==== CR ==== +==== CR - Control register ====
- +
-Control register+
  
 \\ {{clock_reg_cr.svg}} \\ \\ \\ {{clock_reg_cr.svg}} \\ \\
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 |:::|1|X ready| |:::|1|X ready|
  
-==== PLLCFGR ====+==== CSR - Control and status register ====
  
-PLL configuration register+\\ {{clock_reg_csr.svg}} \\ \\ 
 + 
 +|< 100% 5em 5em >| 
 +|LSION|0|Internal low speed clock enabled| 
 +|:::|1|Internal low speed clock disabled (reset state)| 
 +|LSIRDY|0|Internal low speed clock **not** ready| 
 +|:::|1|Internal low speed clock ready (reset state)| 
 + 
 +==== PLLCFGR - PLL configuration register ====
  
 \\ {{clock_reg_pllcfgr.svg}} \\ \\ \\ {{clock_reg_pllcfgr.svg}} \\ \\
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 * Please refer to reference manual (p.162ff) for detailed explanation of register values. \\ \\ * Please refer to reference manual (p.162ff) for detailed explanation of register values. \\ \\
  
-==== CFGR ==== +==== CFGR - Configuration register ====
- +
-Configuration register+
  
 \\ {{clock_reg_cfgr.svg}} \\ \\ \\ {{clock_reg_cfgr.svg}} \\ \\
  
 |< 100% 5em 5em 15em 5em >| |< 100% 5em 5em 15em 5em >|
-|SW|00|HSI as SYSCLK (reset state)| +|SW|00|Enable HSI as SYSCLK (reset state)|| 
-|:::|01|HSE as SYSCLK| +|:::|01|Enable HSE as SYSCLK|| 
-|:::|10|PLL as SYSCLK|+|:::|10|Enable PLL as SYSCLK|| 
 +|SWS|00|HSI used as SYSCLK|| 
 +|:::|01|HSE used as SYSCLK|| 
 +|:::|10|PLL used as SYSCLK||
 |HPRE|0xxx|SYSCLK not divided (reset state)||| |HPRE|0xxx|SYSCLK not divided (reset state)|||
-|:::|1000|HCLK => SYSCLK / 2|1100|HCLK => SYSCLK / 64| +|:::|1000|HCLK => f<sub>SYSCLK</sub> / 2|1100|HCLK => f<sub>SYSCLK</sub> / 64| 
-|:::|1001|HCLK => SYSCLK / 4|1101|HCLK => SYSCLK / 128| +|:::|1001|HCLK => f<sub>SYSCLK</sub> / 4|1101|HCLK => f<sub>SYSCLK</sub> / 128| 
-|:::|1010|HCLK => SYSCLK / 8|1110|HCLK => SYSCLK / 256| +|:::|1010|HCLK => f<sub>SYSCLK</sub> / 8|1110|HCLK => f<sub>SYSCLK</sub> / 256| 
-|:::|1011|HCLK => SYSCLK / 16|1111|HCLK => SYSCLK / 512|+|:::|1011|HCLK => f<sub>SYSCLK</sub> / 16|1111|HCLK => f<sub>SYSCLK</sub> / 512|
 |PPRE1|0xx|HCLK not divided (reset state)||| |PPRE1|0xx|HCLK not divided (reset state)|||
-|:::|1000|PCLK1 => HCLK / 2|1100|PCLK1 => HCLK / 64| +|:::|1000|PCLK1 => f<sub>HCLK</sub> / 2|1100|PCLK1 => f<sub>HCLK</sub> / 64| 
-|:::|1001|PCLK1 => HCLK / 4|1101|PCLK1 => HCLK / 128|+|:::|1001|PCLK1 => f<sub>HCLK</sub> / 4|1101|PCLK1 => f<sub>HCLK</sub> / 128|
 |PPRE2*|0xx|HCLK not divided (reset state)||| |PPRE2*|0xx|HCLK not divided (reset state)|||
-|:::|100|PCLK2 => HCLK / 2|110|PCLK2 => HCLK / 8| +|:::|100|PCLK2 => f<sub>HCLK</sub> / 2|110|PCLK2 => f<sub>HCLK</sub> / 8| 
-|:::|101|PCLK2 => HCLK / 4|111|PCLK2 => HCLK / 16| +|:::|101|PCLK2 => f<sub>HCLK</sub> / 4|111|PCLK2 => f<sub>HCLK</sub> / 16| 
-* if PPRE2 **not** 0xx then TCLK => PCLK2 / 2  \\ \\+* if PPRE2 **not** 0xx then TCLK => f<sub>PCLK2</sub> • 2  \\ \\
  • stm32/peripherals/rcc_clock.1456751682.txt.gz
  • Last modified: 2016/02/29 13:14
  • by feur