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stm32:peripherals:nvic [2017/08/24 08:51] ruanstm32:peripherals:nvic [2022/12/27 18:53] (current) ruan
Line 13: Line 13:
 \\ \\
  
-===== Programming Example ===== 
- 
-For external interrupts via GPIO pins go to the [[exti|EXTI]] page. \\ 
- 
-==== Setup Peripheral (e.g. Timer 2) ==== 
- 
-<code c> 
-#include "reg_stm32f4xx.h" 
- 
-RCC->APB1ENR |= (0x1 << 0u);          /* Enable TIM2 clock. */ 
- 
-/* configure timer */ 
-TIM2->PSC = 84000u - 1u;              /* Counting with f = 84MHz / 84000 = 1MHz */ 
-TIM2->ARR = 512u;                     /* Count to 512 */ 
-TIM2->DIER |= (0x1 << 0u);            /* Enable IRQ */ 
- 
-TIM2->CR1 |= (0x1 << 0u);             /* Start timer */ 
-</code> 
-\\ 
- 
-==== Setup NVIC ==== 
- 
-<code c> 
-#include "reg_stm32f4xx.h" 
- 
-NVIC->ISER[0] |= (0x1 << 28u);        /* Enable TIM2 global interrupt. */ 
-</code> 
-\\ 
  
 ===== Configuration Register ===== ===== Configuration Register =====
Line 47: Line 19:
 ==== NVIC - ISERx ==== ==== NVIC - ISERx ====
  
-=== ISER0 === +=== ISER0 Interrupt set enable register 0 ===
- +
-Interrupt set enable register 1+
  
 \\ {{nvic_reg_iser1.svg}} \\ \\ \\ {{nvic_reg_iser1.svg}} \\ \\
  
-=== ISER1 === +=== ISER1 Interrupt set enable register 1 ===
- +
-Interrupt set enable register 2+
  
 \\ {{nvic_reg_iser2.svg}} \\ \\ \\ {{nvic_reg_iser2.svg}} \\ \\
  
-=== ISER2 === +=== ISER2 Interrupt set enable register 2 ===
- +
-Interrupt set enable register 3+
  
 \\ {{nvic_reg_iser3.svg}} \\ \\ \\ {{nvic_reg_iser3.svg}} \\ \\
Line 71: Line 37:
 ==== NVIC - ICERx ==== ==== NVIC - ICERx ====
  
-=== ICER0 === +=== ICER0 Interrupt clear enable register 0 ===
- +
-Interrupt clear enable register 1+
  
 \\ {{nvic_reg_icer1.svg}} \\ \\ \\ {{nvic_reg_icer1.svg}} \\ \\
  
-=== ICER1 === +=== ICER1 Interrupt clear enable register 1 ===
- +
-Interrupt clear enable register 2+
  
 \\ {{nvic_reg_icer2.svg}} \\ \\ \\ {{nvic_reg_icer2.svg}} \\ \\
  
-=== ICER2 === +=== ICER2 Interrupt clear enable register 2 ===
- +
-Interrupt clear enable register 3+
  
 \\ {{nvic_reg_icer3.svg}} \\ \\ \\ {{nvic_reg_icer3.svg}} \\ \\
Line 92: Line 52:
 |CLRENA*|1|Disable interrupt (mask interrupt)| |CLRENA*|1|Disable interrupt (mask interrupt)|
 //*Setting this bit to 0 has no effect, refer to [[#ISER]]// //*Setting this bit to 0 has no effect, refer to [[#ISER]]//
 +
 +===== Programming Example =====
 +
 +For external interrupts via GPIO pins go to the [[exti|EXTI]] page. \\
 +
 +==== Setup Peripheral (e.g. Timer 2) ====
 +
 +<code c>
 +#include "reg_stm32f4xx.h"
 +
 +RCC->APB1ENR |= (0x1 << 0u);          /* Enable TIM2 clock. */
 +
 +/* configure timer */
 +TIM2->PSC = 84000u - 1u;              /* Counting with f = 84MHz / 84000 = 1MHz */
 +TIM2->ARR = 512u;                     /* Count to 512 */
 +TIM2->DIER |= (0x1 << 0u);            /* Enable IRQ */
 +
 +TIM2->CR1 |= (0x1 << 0u);             /* Start timer */
 +</code>
 +\\
 +
 +==== Setup NVIC ====
 +
 +<code c>
 +#include "reg_stm32f4xx.h"
 +
 +NVIC->ISER0 |= (0x1 << 28u);        /* Enable TIM2 global interrupt. */
 +</code>
 +\\
 +
  • stm32/peripherals/nvic.1503564686.txt.gz
  • Last modified: 2017/08/24 08:51
  • by ruan