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stm32:peripherals:nvic [2016/11/29 13:50] – [NVIC - ICERx] kesr | stm32:peripherals:nvic [2022/12/27 18:53] (current) – ruan | ||
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- | ====== Nested Vectored Interrupt Controller ====== | + | ====== Nested Vectored Interrupt Controller |
The NVIC manages all the interrupts and is closely coupled to the processor core. \\ | The NVIC manages all the interrupts and is closely coupled to the processor core. \\ | ||
Line 13: | Line 13: | ||
\\ | \\ | ||
- | ===== Programming Example ===== | ||
- | |||
- | For external interrupts via GPIO pins go to the [[exti|EXTI]] page. \\ | ||
- | |||
- | ==== Setup Peripheral (e.g. Timer 2) ==== | ||
- | |||
- | <code c> | ||
- | #include " | ||
- | |||
- | RCC-> | ||
- | |||
- | /* configure timer */ | ||
- | TIM2-> | ||
- | TIM2-> | ||
- | TIM2-> | ||
- | |||
- | TIM2-> | ||
- | </ | ||
- | \\ | ||
- | |||
- | ==== Setup NVIC ==== | ||
- | |||
- | <code c> | ||
- | #include " | ||
- | |||
- | NVIC-> | ||
- | </ | ||
- | \\ | ||
===== Configuration Register ===== | ===== Configuration Register ===== | ||
Line 47: | Line 19: | ||
==== NVIC - ISERx ==== | ==== NVIC - ISERx ==== | ||
- | === ISER0 === | + | === ISER0 - Interrupt set enable register |
- | + | ||
- | Interrupt set enable register | + | |
\\ {{nvic_reg_iser1.svg}} \\ \\ | \\ {{nvic_reg_iser1.svg}} \\ \\ | ||
- | === ISER1 === | + | === ISER1 Interrupt set enable register |
- | + | ||
- | Interrupt set enable register | + | |
\\ {{nvic_reg_iser2.svg}} \\ \\ | \\ {{nvic_reg_iser2.svg}} \\ \\ | ||
- | === ISER2 === | + | === ISER2 - Interrupt set enable register |
- | + | ||
- | Interrupt set enable register | + | |
\\ {{nvic_reg_iser3.svg}} \\ \\ | \\ {{nvic_reg_iser3.svg}} \\ \\ | ||
Line 71: | Line 37: | ||
==== NVIC - ICERx ==== | ==== NVIC - ICERx ==== | ||
- | === ICER0 === | + | === ICER0 - Interrupt clear enable register |
- | + | ||
- | Interrupt clear enable register | + | |
\\ {{nvic_reg_icer1.svg}} \\ \\ | \\ {{nvic_reg_icer1.svg}} \\ \\ | ||
- | === ICER1 === | + | === ICER1 - Interrupt clear enable register |
- | + | ||
- | Interrupt clear enable register | + | |
\\ {{nvic_reg_icer2.svg}} \\ \\ | \\ {{nvic_reg_icer2.svg}} \\ \\ | ||
- | === ICER2 === | + | === ICER2 - Interrupt clear enable register |
- | + | ||
- | Interrupt clear enable register | + | |
\\ {{nvic_reg_icer3.svg}} \\ \\ | \\ {{nvic_reg_icer3.svg}} \\ \\ | ||
Line 92: | Line 52: | ||
|CLRENA*|1|Disable interrupt (mask interrupt)| | |CLRENA*|1|Disable interrupt (mask interrupt)| | ||
//*Setting this bit to 0 has no effect, refer to [[#ISER]]// | //*Setting this bit to 0 has no effect, refer to [[#ISER]]// | ||
+ | |||
+ | ===== Programming Example ===== | ||
+ | |||
+ | For external interrupts via GPIO pins go to the [[exti|EXTI]] page. \\ | ||
+ | |||
+ | ==== Setup Peripheral (e.g. Timer 2) ==== | ||
+ | |||
+ | <code c> | ||
+ | #include " | ||
+ | |||
+ | RCC-> | ||
+ | |||
+ | /* configure timer */ | ||
+ | TIM2-> | ||
+ | TIM2-> | ||
+ | TIM2-> | ||
+ | |||
+ | TIM2-> | ||
+ | </ | ||
+ | \\ | ||
+ | |||
+ | ==== Setup NVIC ==== | ||
+ | |||
+ | <code c> | ||
+ | #include " | ||
+ | |||
+ | NVIC-> | ||
+ | </ | ||
+ | \\ | ||
+ |