Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
| stm32:peripherals:nvic [2016/10/06 11:11] – feur | stm32:peripherals:nvic [2022/12/27 18:53] (current) – ruan | ||
|---|---|---|---|
| Line 1: | Line 1: | ||
| - | ====== Nested Vectored Interrupt Controller ====== | + | ====== Nested Vectored Interrupt Controller |
| The NVIC manages all the interrupts and is closely coupled to the processor core. \\ | The NVIC manages all the interrupts and is closely coupled to the processor core. \\ | ||
| Line 12: | Line 12: | ||
| * low-latency exceptions and interrupt handling. | * low-latency exceptions and interrupt handling. | ||
| \\ | \\ | ||
| + | |||
| + | |||
| + | ===== Configuration Register ===== | ||
| + | |||
| + | Table of interrupt numbers: [[interrupt_table| IRQ numbers]]. \\ \\ | ||
| + | ==== NVIC - ISERx ==== | ||
| + | |||
| + | === ISER0 - Interrupt set enable register 0 === | ||
| + | |||
| + | \\ {{nvic_reg_iser1.svg}} \\ \\ | ||
| + | |||
| + | === ISER1 Interrupt set enable register 1 === | ||
| + | |||
| + | \\ {{nvic_reg_iser2.svg}} \\ \\ | ||
| + | |||
| + | === ISER2 - Interrupt set enable register 2 === | ||
| + | |||
| + | \\ {{nvic_reg_iser3.svg}} \\ \\ | ||
| + | |||
| + | |< 100% 5em 5em >| | ||
| + | |SETENA*|1|Enable interrupt (unmask interrupt)| | ||
| + | //*Setting this bit to 0 has no effect, refer to [[#ICER]]// \\ | ||
| + | |||
| + | ==== NVIC - ICERx ==== | ||
| + | |||
| + | === ICER0 - Interrupt clear enable register 0 === | ||
| + | |||
| + | \\ {{nvic_reg_icer1.svg}} \\ \\ | ||
| + | |||
| + | === ICER1 - Interrupt clear enable register 1 === | ||
| + | |||
| + | \\ {{nvic_reg_icer2.svg}} \\ \\ | ||
| + | |||
| + | === ICER2 - Interrupt clear enable register 2 === | ||
| + | |||
| + | \\ {{nvic_reg_icer3.svg}} \\ \\ | ||
| + | |||
| + | |< 100% 5em 5em >| | ||
| + | |CLRENA*|1|Disable interrupt (mask interrupt)| | ||
| + | //*Setting this bit to 0 has no effect, refer to [[#ISER]]// | ||
| ===== Programming Example ===== | ===== Programming Example ===== | ||
| Line 38: | Line 78: | ||
| #include " | #include " | ||
| - | NVIC->ISER[0] | + | NVIC->ISER0 |= (0x1 << 28u); /* Enable TIM2 global interrupt. */ |
| </ | </ | ||
| \\ | \\ | ||
| - | ===== Configuration Register ===== | ||
| - | |||
| - | ==== ISER ==== | ||
| - | |||
| - | Interrupt set enable register | ||
| - | |||
| - | \\ {{nvic_reg_iser.svg}} \\ \\ | ||
| - | |||
| - | |< 100% 5em 5em >| | ||
| - | |SETENA*|1|Enable interrupt (unmask interrupt)| | ||
| - | //*Setting this bit to 0 has no effect, refer to [[#ICER]]// \\ | ||
| - | |||
| - | ==== ICER ==== | ||
| - | |||
| - | Interrupt clear enable register | ||
| - | |||
| - | \\ {{nvic_reg_icer.svg}} \\ \\ | ||
| - | |||
| - | |< 100% 5em 5em >| | ||
| - | |CLRENA*|1|Disable interrupt (mask interrupt)| | ||
| - | //*Setting this bit to 0 has no effect, refer to [[#ISER]]// | ||