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stm32:peripherals:nvic [2016/10/06 09:46] – created feurstm32:peripherals:nvic [2022/12/27 18:53] (current) – ruan
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-====== Nested Vectored Interrupt Controller ======+====== Nested Vectored Interrupt Controller (NVIC) ======
  
 The NVIC manages all the interrupts and is closely coupled to the processor core. \\ The NVIC manages all the interrupts and is closely coupled to the processor core. \\
 +A list of all available interrupts: [[interrupt_table|interrupt table]]. \\
  
 \\ {{nvic_complete.svg?700em}} \\ \\ \\ {{nvic_complete.svg?700em}} \\ \\
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   * 16 programmable priority levels.   * 16 programmable priority levels.
   * low-latency exceptions and interrupt handling.   * low-latency exceptions and interrupt handling.
 +\\
 +
 +
 +===== Configuration Register =====
 +
 +Table of interrupt numbers: [[interrupt_table| IRQ numbers]]. \\ \\
 +==== NVIC - ISERx ====
 +
 +=== ISER0 - Interrupt set enable register 0 ===
 +
 +\\ {{nvic_reg_iser1.svg}} \\ \\
 +
 +=== ISER1 Interrupt set enable register 1 ===
 +
 +\\ {{nvic_reg_iser2.svg}} \\ \\
 +
 +=== ISER2 - Interrupt set enable register 2 ===
 +
 +\\ {{nvic_reg_iser3.svg}} \\ \\
 +
 +|< 100% 5em 5em >|
 +|SETENA*|1|Enable interrupt (unmask interrupt)|
 +//*Setting this bit to 0 has no effect, refer to [[#ICER]]// \\
 +
 +==== NVIC - ICERx ====
 +
 +=== ICER0 - Interrupt clear enable register 0 ===
 +
 +\\ {{nvic_reg_icer1.svg}} \\ \\
 +
 +=== ICER1 - Interrupt clear enable register 1 ===
 +
 +\\ {{nvic_reg_icer2.svg}} \\ \\
 +
 +=== ICER2 - Interrupt clear enable register 2 ===
 +
 +\\ {{nvic_reg_icer3.svg}} \\ \\
 +
 +|< 100% 5em 5em >|
 +|CLRENA*|1|Disable interrupt (mask interrupt)|
 +//*Setting this bit to 0 has no effect, refer to [[#ISER]]//
 +
 +===== Programming Example =====
 +
 +For external interrupts via GPIO pins go to the [[exti|EXTI]] page. \\
 +
 +==== Setup Peripheral (e.g. Timer 2) ====
 +
 +<code c>
 +#include "reg_stm32f4xx.h"
 +
 +RCC->APB1ENR |= (0x1 << 0u);          /* Enable TIM2 clock. */
 +
 +/* configure timer */
 +TIM2->PSC = 84000u - 1u;              /* Counting with f = 84MHz / 84000 = 1MHz */
 +TIM2->ARR = 512u;                     /* Count to 512 */
 +TIM2->DIER |= (0x1 << 0u);            /* Enable IRQ */
 +
 +TIM2->CR1 |= (0x1 << 0u);             /* Start timer */
 +</code>
 +\\
 +
 +==== Setup NVIC ====
 +
 +<code c>
 +#include "reg_stm32f4xx.h"
 +
 +NVIC->ISER0 |= (0x1 << 28u);        /* Enable TIM2 global interrupt. */
 +</code>
 +\\
  
-===== Functions ===== 
  • stm32/peripherals/nvic.1475747209.txt.gz
  • Last modified: 2016/10/06 09:46
  • by feur