Differences
This shows you the differences between two versions of the page.
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stm32:peripherals:interrupt_table [2016/03/02 13:55] – created feur | stm32:peripherals:interrupt_table [2016/10/03 09:43] (current) – feur | ||
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|< 100% 5em 5em 10em 10em >| | |< 100% 5em 5em 10em 10em >| | ||
^ IRQ ^ Priority | ^ IRQ ^ Priority | ||
- | | | -3 | Reset | 0x0000' | + | | | -3* | Reset | 0x0000' |
- | | | -2 | NMI | 0x0000' | + | | | -2* | NMI | 0x0000' |
- | | | -1 | HardFault | 0x0000' | + | | | -1* | HardFault | 0x0000' |
| | 0 | MemManage | 0x0000' | | | 0 | MemManage | 0x0000' | ||
| | 1 | BusFault | 0x0000' | | | 1 | BusFault | 0x0000' | ||
Line 11: | Line 11: | ||
| | 3 | SVCall | 0x0000' | | | 3 | SVCall | 0x0000' | ||
| | 4 | Debug Monitor | 0x0000' | | | 4 | Debug Monitor | 0x0000' | ||
- | | | 5 | PendSV | 0x0000' | + | | | 5 | PendSV | 0x0000' |
- | | | 6 | SysTick | 0x0000' | + | | | 6 | [[SysTick]] | 0x0000' |
| 0 | 7 | WWDG | 0x0000' | | 0 | 7 | WWDG | 0x0000' | ||
- | | 1 | 8 | PVD | 0x0000' | + | | 1 | 8 | PVD | 0x0000' |
| 2 | 9 | TP_TS | 0x0000' | | 2 | 9 | TP_TS | 0x0000' | ||
| 3 | 10 | RTC_WKUP | 0x0000' | | 3 | 10 | RTC_WKUP | 0x0000' | ||
| 4 | 11 | FLASH | 0x0000' | | 4 | 11 | FLASH | 0x0000' | ||
- | | 5 | 12 | RCC | 0x0000' | + | | 5 | 12 | [[RCC]] | 0x0000' |
- | | 6 | 13 | EXTI0 | 0x0000' | + | | 6 | 13 |
- | | 7 | 14 | EXTI1 | 0x0000' | + | | 7 | 14 |
- | | 8 | 15 | EXTI2 | 0x0000' | + | | 8 | 15 |
- | | 9 | 16 | EXTI3 | 0x0000' | + | | 9 | 16 |
- | | 10 | 17 | EXTI4 | 0x0000' | + | | 10 | 17 |
- | | 11 | 18 | DMA1_Stream0 | 0x0000' | + | | 11 | 18 | DMA1_Stream0 | 0x0000' |
- | | 12 | 19 | DMA1_Stream1 | 0x0000' | + | | 12 | 19 | DMA1_Stream1 | 0x0000' |
- | | 13 | 20 | DMA1_Stream2 | 0x0000' | + | | 13 | 20 | DMA1_Stream2 | 0x0000' |
- | | 14 | 21 | DMA1_Stream3 | 0x0000' | + | | 14 | 21 | DMA1_Stream3 | 0x0000' |
- | | 15 | 22 | DMA1_Stream4 | 0x0000' | + | | 15 | 22 | DMA1_Stream4 | 0x0000' |
- | | 16 | 23 | DMA1_Stream5 | 0x0000' | + | | 16 | 23 | DMA1_Stream5 | 0x0000' |
- | | 17 | 24 | DMA1_Stream6 | 0x0000' | + | | 17 | 24 | DMA1_Stream6 | 0x0000' |
- | | 18 | 25 | ADC | 0x0000' | + | | 18 | 25 | [[ADC]] | 0x0000' |
| 19 | 26 | CAN1_TX | 0x0000' | | 19 | 26 | CAN1_TX | 0x0000' | ||
| 20 | 27 | CAN1_RX0 | 0x0000' | | 20 | 27 | CAN1_RX0 | 0x0000' | ||
| 21 | 28 | CAN1_RX1 | 0x0000' | | 21 | 28 | CAN1_RX1 | 0x0000' | ||
| 22 | 29 | CAN1_SCE | 0x0000' | | 22 | 29 | CAN1_SCE | 0x0000' | ||
- | | 23 | 30 | EXTI9_5 | 0x0000' | + | | 23 | 30 |
- | | 24 | 31 | TIM1_BRK_TIM9 | + | | 24 | 31 | TIM1_BRK \\ TIM9 | 0x0000' |
- | | 25 | 32 | TIM1_UP_TIM10 | + | | 25 | 32 | TIM1_UP \\ TIM10 | 0x0000' |
- | | 26 | 33 | TIM1_TRG_COM_TIM11 | + | | 26 | 33 | TIM1_TRG_COM \\ TIM11 | 0x0000' |
- | | 27 | 34 | TIM1_CC | 0x0000' | + | | 27 | 34 | TIM1_CC | 0x0000' |
- | | 28 | 35 | TIM2 | 0x0000' | + | | 28 | 35 |
- | | 29 | 36 | TIM3 | 0x0000' | + | | 29 | 36 |
- | | 30 | 37 | TIM4 | 0x0000' | + | | 30 | 37 |
- | | 31 | 38 | I2C1_EV | 0x0000' | + | | 31 | 38 | I2C1_EV | 0x0000' |
- | | 32 | 39 | I2C1_ER | 0x0000' | + | | 32 | 39 | I2C1_ER | 0x0000' |
- | | 33 | 40 | I2C2_EV | 0x0000' | + | | 33 | 40 | I2C2_EV | 0x0000' |
- | | 34 | 41 | I2C2_ER | 0x0000' | + | | 34 | 41 | I2C2_ER | 0x0000' |
- | | 35 | 42 | SPI1 | 0x0000' | + | | 35 | 42 |
- | | 36 | 43 | SPI2 | 0x0000' | + | | 36 | 43 |
- | | 37 | 44 | USART1 | 0x0000' | + | | 37 | 44 |
- | | 38 | 45 | USART2 | 0x0000' | + | | 38 | 45 |
- | | 39 | 46 | USART3 | 0x0000' | + | | 39 | 46 |
- | | 40 | 47 | EXTI15_10 | 0x0000' | + | | 40 | 47 |
- | | 41 | 48 | RTC_Alarm | 0x0000' | + | | 41 | 48 | RTC_Alarm | 0x0000' |
- | | 42 | 49 | USB_FS_WKUP | 0x0000' | + | | 42 | 49 | USB_FS_WKUP | 0x0000' |
- | | 43 | 50 | TIM8_BRK_TIM12 | + | | 43 | 50 | TIM8_BRK \\ TIM12 | 0x0000' |
- | | 44 | 51 | TIM8_UP_TIM13 | + | | 44 | 51 | TIM8_UP \\ TIM13 | 0x0000' |
- | | 45 | 52 | TIM8_TRG_COM_TIM14 | + | | 45 | 52 | TIM8_TRG_COM \\ TIM14 | 0x0000' |
- | | 46 | 53 | TIM8_CC | 0x0000' | + | | 46 | 53 | TIM8_CC | 0x0000' |
- | | 47 | 54 | DMA1_Stream7 | 0x0000' | + | | 47 | 54 | DMA1_Stream7 | 0x0000' |
- | | 48 | 55 | FMC | 0x0000' | + | | 48 | 55 | FMC | 0x0000' |
- | | 49 | 56 | SDIO | 0x0000' | + | | 49 | 56 | SDIO | 0x0000' |
- | | 50 | 57 | TIM5 | 0x0000' | + | | 50 | 57 |
- | | 51 | 58 | SPI3 | 0x0000' | + | | 51 | 58 |
- | | 52 | 59 | UART4 | 0x0000' | + | | 52 | 59 |
- | | 53 | 60 | UART5 | 0x0000' | + | | 53 | 60 |
- | | 54 | 61 | TIM6_DAC | + | | 54 | 61 | TIM6 \\ [[DAC]] |
- | | 55 | 62 | TIM7 | 0x0000' | + | | 55 | 62 | TIM7 | 0x0000' |
- | | 56 | 63 | DMA2_Stream0 | 0x0000' | + | | 56 | 63 | DMA2_Stream0 | 0x0000' |
- | | 57 | 64 | DMA2_Stream1 | 0x0000' | + | | 57 | 64 | DMA2_Stream1 | 0x0000' |
- | | 58 | 65 | DMA2_Stream2 | 0x0000' | + | | 58 | 65 | DMA2_Stream2 | 0x0000' |
- | | 59 | 66 | DMA2_Stream3 | 0x0000' | + | | 59 | 66 | DMA2_Stream3 | 0x0000' |
- | | 60 | 67 | DMA2_Stream4 | 0x0000' | + | | 60 | 67 | DMA2_Stream4 | 0x0000' |
- | | 61 | 68 | ETH | 0x0000' | + | | 61 | 68 | ETH | 0x0000' |
- | | 62 | 69 | ETH_WKUP | 0x0000' | + | | 62 | 69 | ETH_WKUP | 0x0000' |
| 63 | 70 | CAN2_TX | 0x0000' | | 63 | 70 | CAN2_TX | 0x0000' | ||
| 64 | 71 | CAN2_RX0 | 0x0000' | | 64 | 71 | CAN2_RX0 | 0x0000' | ||
| 65 | 72 | CAN2_RX1 | 0x0000' | | 65 | 72 | CAN2_RX1 | 0x0000' | ||
| 66 | 73 | CAN2_SCE | 0x0000' | | 66 | 73 | CAN2_SCE | 0x0000' | ||
- | | 67 | 74 | USB_FS | 0x0000' | + | | 67 | 74 | USB_FS | 0x0000' |
- | | 68 | 75 | DMA2_Stream5 | 0x0000' | + | | 68 | 75 | DMA2_Stream5 | 0x0000' |
- | | 69 | 76 | DMA2_Stream6 | 0x0000' | + | | 69 | 76 | DMA2_Stream6 | 0x0000' |
- | | 70 | 77 | DMA2_Stream7 | 0x0000' | + | | 70 | 77 | DMA2_Stream7 | 0x0000' |
- | | 71 | 78 | USART6 | 0x0000' | + | | 71 | 78 |
- | | 72 | 79 | I2C3_EV | 0x0000' | + | | 72 | 79 | I2C3_EV | 0x0000' |
- | | 73 | 80 | I2C3_ER | 0x0000' | + | | 73 | 80 | I2C3_ER | 0x0000' |
- | | 74 | 81 | USB_HS_EP1_OUT | 0x0000' | + | | 74 | 81 | USB_HS_EP1_OUT | 0x0000' |
- | | 75 | 82 | USB_HS_EP1_IN | 0x0000' | + | | 75 | 82 | USB_HS_EP1_IN | 0x0000' |
- | | 76 | 83 | USB_HS_WKUP | 0x0000' | + | | 76 | 83 | USB_HS_WKUP | 0x0000' |
- | | 77 | 84 | USB_HS | 0x0000' | + | | 77 | 84 | USB_HS | 0x0000' |
- | | 78 | 85 | DCMI | 0x0000' | + | | 78 | 85 | DCMI | 0x0000' |
- | | 79 | 86 | CRYPT | 0x0000' | + | | 79 | 86 | CRYPT | 0x0000' |
- | | 80 | 87 | HASH_RNG | 0x0000' | + | | 80 | 87 | HASH_RNG | 0x0000' |
- | | 81 | 88 | FPU | 0x0000' | + | | 81 | 88 | FPU | 0x0000' |
- | | 82 | 89 | UART7 | 0x0000' | + | | 82 | 89 |
- | | 83 | 90 | UART8 | 0x0000' | + | | 83 | 90 |
- | | 84 | 91 | SPI4 | 0x0000' | + | | 84 | 91 |
- | | 85 | 92 | SPI5 | 0x0000' | + | | 85 | 92 |
- | | 86 | 93 | SPI6 | 0x0000' | + | | 86 | 93 |
- | | 87 | 94 | SAI1 | 0x0000' | + | | 87 | 94 | SAI1 | 0x0000' |
- | | 88 | 95 | LCD | 0x0000' | + | | 88 | 95 | LCD | 0x0000' |
- | | 89 | 96 | LCD_ERR | 0x0000' | + | | 89 | 96 | LCD_ERR | 0x0000' |
- | | 90 | 97 | DMA2D | 0x0000' | + | | 90 | 97 | DMA2D | 0x0000' |
+ | |||
+ | * Priority **not** changeable |