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stm32:peripherals:gpio_output [2016/02/25 08:33] – feur | stm32:peripherals:gpio_output [2022/12/28 08:17] (current) – ruan | ||
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\\ {{gpio_output.svg}} \\ \\ | \\ {{gpio_output.svg}} \\ \\ | ||
- | ===== Programming | + | ===== Programming |
- | The code snippet bellow shows how to configure and use a GPIO pin as output. | + | ==== Enable Peripheral ==== |
- | <code c> | + | Make sure the peripheral is enabled: |
- | #include " | + | * Enable GPIOx in '' |
- | /* Configure GPIO pin A.5 as output. */ | + | ==== Setup output |
- | GPIOA-> | + | |
- | GPIOA-> | + | |
- | GPIOA->PUPDR &= ~(0x3 << 10u); /* Clear existing | + | Configure the MODE and PUPDR as well as the output type and speed register, \\ for every pin that should act as digital output: |
- | GPIOA-> | + | * Write '' |
- | + | | |
- | GPIOA-> | + | |
- | + | | |
- | GPIOA->OSPEEDR &= ~(0x3 << 10u); /* Clear existing | + | |
- | GPIOA-> | + | |
- | + | ||
- | /* Write to GPIO pin A.5. */ | + | |
- | GPIOA-> | + | |
- | + | ||
- | GPIOA-> | + | |
- | GPIOA-> | + | |
- | </ | + | |
\\ | \\ | ||
===== Configuration Registers ===== | ===== Configuration Registers ===== | ||
- | ==== MODER ==== | + | ==== GPIOx_MODER - Port mode register |
- | + | ||
- | Mode register | + | |
\\ {{gpio_reg_common.svg}} \\ \\ | \\ {{gpio_reg_common.svg}} \\ \\ | ||
|< 100% 5em 5em >| | |< 100% 5em 5em >| | ||
- | |Pinx|01|Output mode (reset state)| | + | |Pin x|01|Output mode| |
- | ==== PUPDR ==== | + | ==== GPIOx_PUPDR - Port pull-up / pull-down register |
- | + | ||
- | Push-up / pull-down register | + | |
\\ {{gpio_reg_common.svg}} \\ \\ | \\ {{gpio_reg_common.svg}} \\ \\ | ||
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|::: | |::: | ||
|::: | |::: | ||
+ | |::: | ||
- | ==== OTYPER | + | ==== GPIOx_OTYPER - Port output type register |
- | + | ||
- | Output type register | + | |
\\ {{gpio_reg_otyper.svg}} \\ \\ | \\ {{gpio_reg_otyper.svg}} \\ \\ | ||
Line 69: | Line 53: | ||
|::: | |::: | ||
- | ==== OSPEEDR | + | ==== GPIOx_OSPEEDR - Port output speed register |
- | + | ||
- | Output speed register | + | |
\\ {{gpio_reg_common.svg}} \\ \\ | \\ {{gpio_reg_common.svg}} \\ \\ | ||
Line 83: | Line 65: | ||
===== Data Registers ===== | ===== Data Registers ===== | ||
- | ==== ODR ==== | + | ==== GPIOx_ODR - Port output data register |
- | + | ||
- | Output data register | + | |
\\ {{gpio_reg_odr.svg}} \\ \\ | \\ {{gpio_reg_odr.svg}} \\ \\ | ||
- | ==== BSRR ==== | + | |< 100% 5em 5em >| |
+ | |ODx|0|Clear/ | ||
+ | |:::|1|Set pin x| | ||
- | Bit set / reset register | + | ==== GPIOx_BSRR Port bit set / reset register |
\\ {{gpio_reg_bsrr.svg}} \\ \\ | \\ {{gpio_reg_bsrr.svg}} \\ \\ | ||
|< 100% 5em 5em >| | |< 100% 5em 5em >| | ||
- | |BSx|1|Set pin x| | + | |BSx|0|No effect| |
- | |BRx|1|Clear/ | + | |:::|1|Set pin x| |
- | + | |BRx|0|No effext| | |
- | ===== Legend ===== | + | |:::|1|Clear/ |
- | \\ {{legende.svg}} \\ \\ |