Differences

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--- stm32:peripherals:dma_connection [2016/10/06 08:09] – feur
+++ stm32:peripherals:dma_connection [2022/12/28 07:53] (current) – [Periphery/Memory Interface] ruan
@@ Line 9: / Line 9: @@
 ===== DMA controller 1 =====
-==== Periphery Interface ====
+==== Peripheral Interface ====
-On the periphery interface the following marked peripherals are accessible. \\
+On the peripheral interface the following marked peripherals are accessible. \\
 The <color red>red</color> peripherals can request a DMA transfer (see table below). \\
@@ Line 35: / Line 35: @@
 ===== DMA controller 2 =====
-==== Periphery Interface ====
+==== Peripheral/Memory Interface ====
-On the periphery interface the following marked peripherals are accessible. \\
+This DMA controller can access the same peripherals on the memory interface as on the peripheral interface. \\
-This DMA controller can also access most memory on the periphery interface. \\
 The <color red>red</color> peripherals can request a DMA transfer (see table below). \\
-\\ {{dma2_periphery.svg?350em}} \\ \\
+\\ {{dma2_mem_per.svg?350em}} \\ \\
 |< 100% 7em >|
@@ Line 53: / Line 52: @@
 ^ Channel 6 | TIM1 TRG | TIM1 Ch. 1 | TIM1 Ch. 2 | TIM1 Ch. 1 | TIM1 TRG \\ TIM1 COM \\ TIM1 Ch. 4 | TIM1 Up | TIM1 Ch. 3 | |
 ^ Channel 7 | | TIM8 Up | TIM8 Ch. 1 | TIM8 Ch. 2 | TIM8 Ch. 3 | SPI5 RX | SPI5 TX | TIM8 TRG \\ TIM8 COM \\ TIM8 Ch. 4 |
-==== Memory Interface ====
-On the memory interface the following marked peripherals are accessible. \\
-\\ {{dma2_memory.svg?350em}} \\ \\