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| Both sides previous revision Previous revision Next revision | Previous revision | ||
| stm32:peripherals:dma_connection [2016/10/06 07:57] – feur | stm32:peripherals:dma_connection [2022/12/28 07:53] (current) – [Periphery/Memory Interface] ruan | ||
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| Each DMA controller is connected to the rest of the system in a different way. \\ | Each DMA controller is connected to the rest of the system in a different way. \\ | ||
| + | For memory to memory transfers you should use the DMA controller 2! \\ | ||
| \\ {{dma1_matrix.svg? | \\ {{dma1_matrix.svg? | ||
| Line 8: | Line 9: | ||
| ===== DMA controller 1 ===== | ===== DMA controller 1 ===== | ||
| - | ==== Periphery | + | ==== Peripheral |
| - | On the periphery | + | On the peripheral |
| The <color red> | The <color red> | ||
| - | \\ {{dma1_periphery.svg? | + | \\ {{dma1_periphery.svg? |
| |< 100% 7em >| | |< 100% 7em >| | ||
| Line 26: | Line 27: | ||
| ^ Channel 7 | | TIM6 Up | I2C2 RX | I2C2 RX | USART3 TX | DAC1 | DAC2 | I2C2 TX | | ^ Channel 7 | | TIM6 Up | I2C2 RX | I2C2 RX | USART3 TX | DAC1 | DAC2 | I2C2 TX | | ||
| - | ==== DMA2 ==== | + | ==== Memory Interface |
| - | \\ {{?700em}} \\ \\ | + | On the memory interface the following marked peripherals are accessible. \\ |
| + | |||
| + | \\ {{dma1_memory.svg? | ||
| + | |||
| + | ===== DMA controller 2 ===== | ||
| + | |||
| + | ==== Peripheral/ | ||
| + | |||
| + | This DMA controller can access the same peripherals on the memory interface as on the peripheral interface. \\ | ||
| + | The <color red> | ||
| + | |||
| + | \\ {{dma2_mem_per.svg?350em}} \\ \\ | ||
| |< 100% 7em >| | |< 100% 7em >| | ||