Differences

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--- stm32:peripherals:dma [2016/11/21 06:47] – [Programming Example] feur
+++ stm32:peripherals:dma [2022/12/28 07:50] (current) – ruan
@@ Line 1: / Line 1: @@
 ====== Direct Memory Access ======
-The two DMA controller can be used to quickly transfer data between two peripherals (or memory) without any CPU interaction. \\
+The two DMA controllers can be used to quickly transfer data between two peripherals (or memory) without any CPU interaction. \\
-Not all combination of peripherals are possible: available [[dma_connection|DMA connections]]. \\
+Not all combinations of peripherals are possible: available [[dma_connection|DMA connections]]. \\
 \\ {{dma_complete.svg?700em}} \\ \\
@@ Line 9: / Line 9: @@
   * 8 streams for each DMA controller, up to 8 channels per stream.
-  * 4 (32 bit wide) FIFO buffer per stream.
+  * 4 (32 bit wide) FIFO buffers per stream.
   * Programmable priority.
-\\
-===== Programming Example =====
-The code snippet bellow shows how to configure and use the DMA controller.
-<code c>
-#include "reg_stm32f4xx.h"
-RCC->AHBENR[0] |= (0x1 << 22u);      /* Enable DMA2 clock */
-/* Configure DMA2 controller. */
-DMA2->STREAM[0].CR |= (2u << 25u);   /* Setup channel. */
-DMA2->STREAM[0].CR |= (0x0 << 6u);   /* Setup direction. */
-DMA2->STREAM[0].CR |= (0x1 << 8u);   /* Setup circular mode. */
-DMA2->STREAM[0].NDTR |= 1u;          /* Setup nr of transfers. */
-/* Setup source and destination. */
-DMA2->STREAM[0].PAR |= (uint32_t) &(ADC3->DR);
-DMA2->STREAM[0].M0AR |= (uint32_t) &(TIM3->CCR[0]);
-/* Setup buffer size. */
-DMA2->STREAM[0].CR |= (0x1 << 11u);  /* PSIZE */
-DMA2->STREAM[0].CR |= (0x1 << 13u);  /* MSIZE */
-/* Start DMA transfer. */
-DMA2->STREAM[0].CR |= (0x1 << 0u);
-</code>
-\\
-> {{logo_hal.svg?72px |}} **Hardware Abstraction Layer**
-> [[https://ennis.zhaw.ch/hal/structreg__dma__t.html | Register Types]]
-> [[https://ennis.zhaw.ch/hal/hal__dma_8h.html | InES DMA HAL Interface]]
 \\
 ===== Configuration Registers =====
-==== SxCR ====
+==== DMA_SxCR - Stream X configuration register ====
-Stream X configuration register
 \\ {{dma_reg_sxcr.svg}} \\ \\
@@ Line 76: / Line 40: @@
 * Only writeable if EN = '0' \\ \\
-==== SxPAR ====
+==== DMA_SxPAR - Stream X peripheral address register ====
-Stream X peripheral address register
 \\ {{dma_reg_sxpar.svg}} \\ \\
@@ Line 85: / Line 47: @@
 |NDT|xxx|Number of data items to be transfered.|
-==== SxM0AR ====
+==== DMA_SxM0AR - Stream X memory 0 address register====
-Stream X memory 0 address register
 \\ {{dma_reg_sxm0ar.svg}} \\ \\
@@ Line 94: / Line 54: @@
 |M0A|xxx|Base address of memory 0.|
-==== SxM1AR ====
+==== DMA_SxM1AR - Stream X memory 1 address register ====
-Stream X memory 1 address register
 \\ {{dma_reg_sxm1ar.svg}} \\ \\
@@ Line 103: / Line 61: @@
 |M1A|xxx|Base address of memory 1.|
-==== SxNDTR ====
+==== DMA_SxNDTR - Stream X number of data register ====
-Stream X number of data register
 \\ {{dma_reg_sxndtr.svg}} \\ \\
@@ Line 111: / Line 67: @@
 |< 100% 5em >|
 |NDT|xxx|Number of data items to be transfered.|
+===== Programming Example =====
+The code snippet below shows how to configure and use the DMA controller.
+<code c>
+#include "reg_stm32f4xx.h"
+RCC->AHBENR[0] |= (0x1 << 22u);      /* Enable DMA2 clock */
+/* Configure DMA2 controller. */
+DMA2->STREAM[0].CR |= (2u << 25u);   /* Setup channel. */
+DMA2->STREAM[0].CR |= (0x0 << 6u);   /* Setup direction. */
+DMA2->STREAM[0].CR |= (0x1 << 8u);   /* Setup circular mode. */
+DMA2->STREAM[0].NDTR |= 1u;          /* Setup nr of transfers. */
+/* Setup source and destination. */
+DMA2->STREAM[0].PAR |= (uint32_t) &(ADC3->DR);
+DMA2->STREAM[0].M0AR |= (uint32_t) &(TIM3->CCR[0]);
+/* Setup buffer size. */
+DMA2->STREAM[0].CR |= (0x1 << 11u);  /* PSIZE */
+DMA2->STREAM[0].CR |= (0x1 << 13u);  /* MSIZE */
+/* Start DMA transfer. */
+DMA2->STREAM[0].CR |= (0x1 << 0u);
+</code>
+\\