Differences

This shows you the differences between two versions of the page.

--- stm32:peripherals:dma [2016/09/22 07:50] – feur
+++ stm32:peripherals:dma [2022/12/28 07:50] (current) – ruan
@@ Line 1: / Line 1: @@
 ====== Direct Memory Access ======
-The two DMA controller can be used to quickly transfer data between two peripherals (or memory) without any CPU interaction. \\
+The two DMA controllers can be used to quickly transfer data between two peripherals (or memory) without any CPU interaction. \\
+Not all combinations of peripherals are possible: available [[dma_connection|DMA connections]]. \\
 \\ {{dma_complete.svg?700em}} \\ \\
@@ Line 8: / Line 9: @@
   * 8 streams for each DMA controller, up to 8 channels per stream.
-  * 4 (32 bit wide) FIFO buffer per stream.
+  * 4 (32 bit wide) FIFO buffers per stream.
   * Programmable priority.
 \\
+===== Configuration Registers =====
+==== DMA_SxCR - Stream X configuration register ====
+\\ {{dma_reg_sxcr.svg}} \\ \\
+|< 100% 5em 5em 15em 5em >|
+|EN|0|Stream disabled (reset state)||
+|:::|1|Stream enabled (reset state)||
+|CHSEL|xxx|Channel nr selected (0..7)||
+|CIR|0|Circular mode disabled (reset state)||
+|:::|1|Circular mode enabled||
+|DIR|00|Direction peripheral to memory (reset state)||
+|:::|01|Direction memory to peripheral||
+|:::|10|Direction memory to memory||
+|:::|11|reserved||
+|PSIZE*|00|Peripheral size 8 bit (reset state)||
+|:::|01|Peripheral size 16 bit||
+|:::|10|Peripheral size 32 bit||
+|:::|11|reserved||
+|MSIZE*|00|Memory size 8 bit (reset state)||
+|:::|01|Memory size 16 bit||
+|:::|10|Memory  size 32 bit||
+|:::|11|reserved||
+* Only writeable if EN = '0' \\ \\
+==== DMA_SxPAR - Stream X peripheral address register ====
+\\ {{dma_reg_sxpar.svg}} \\ \\
+|< 100% 5em >|
+|NDT|xxx|Number of data items to be transfered.|
+==== DMA_SxM0AR - Stream X memory 0 address register====
+\\ {{dma_reg_sxm0ar.svg}} \\ \\
+|< 100% 5em >|
+|M0A|xxx|Base address of memory 0.|
+==== DMA_SxM1AR - Stream X memory 1 address register ====
+\\ {{dma_reg_sxm1ar.svg}} \\ \\
+|< 100% 5em >|
+|M1A|xxx|Base address of memory 1.|
+==== DMA_SxNDTR - Stream X number of data register ====
+\\ {{dma_reg_sxndtr.svg}} \\ \\
+|< 100% 5em >|
+|NDT|xxx|Number of data items to be transfered.|
 ===== Programming Example =====
-The code snippet bellow shows how to configure and use the DMA controller.
+The code snippet below shows how to configure and use the DMA controller.
 <code c>
@@ Line 40: / Line 96: @@
 </code>
 \\
-> {{logo_hal.svg?72px |}} **Hardware Abstraction Layer**
-> [[https://ennis.zhaw.ch/hal/structreg__dma__t.html | Registry Types]]
-> [[https://ennis.zhaw.ch/hal/hal__dma_8h.html | InES DMA HAL Interface]]
-\\
-===== Configuration Registers =====
-==== SxCR ====
-Stream X configuration register
-\\ {{dma_reg_sxcr.svg}} \\ \\
-|< 100% 5em 5em 15em 5em >|
-|MSTR|0|Slave mode (reset state)||
-|:::|1|Master mode||
-|BR|000|BR => f<sub>PCLK2</sub> / 2 (reset state)|100|BR => f<sub>PCLK2</sub> / 32|
-|:::|001|BR => f<sub>PCLK2</sub> / 4|101|BR => f<sub>PCLK2</sub> / 64|
-|:::|010|BR => f<sub>PCLK2</sub> / 8|110|BR => f<sub>PCLK2</sub> / 128|
-|:::|011|BR => f<sub>PCLK2</sub> / 16|111|BR => f<sub>PCLK2</sub> / 256|
-|SPE|0|SPI disabled (reset state)||
-|:::|1|SPI enabled||
-|LSBFIRST|0|MSB transmitted first (reset state)||
-|:::|1|LSB transmitted first||
-|SSM|0|Slave management by hw (reset state)||
-|:::|1|Slave management by sw||
-|DFF|0|Data frame: 8 bit (reset state)||
-|:::|1|Data frame: 16 bit||