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stm32:peripherals:adc [2016/03/02 10:51] – feurstm32:peripherals:adc [2022/12/28 08:11] (current) – ruan
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 The ADC of the STM32F429ZI has a 12 bit resolution and up to 19 multiplexed channels. \\ The ADC of the STM32F429ZI has a 12 bit resolution and up to 19 multiplexed channels. \\
-A analog watchdog monitores the input voltage an can take action if necessary. \\ \\+An analog watchdog monitors the input voltage and can take action if necessary. \\ \\
    
 \\ {{adc_complete.svg}} \\ \\ \\ {{adc_complete.svg}} \\ \\
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   * DMA and Interrupt support.   * DMA and Interrupt support.
 \\ \\
 +===== Configuration Registers =====
  
-===== Programming Example =====+==== ADC_CCR - Common control register ====
  
-<code c> +\\ {{adc_reg_ccr.svg}} \\ \\
-#include "reg_stm32f4xx.h"+
  
-RCC->AHB1ENR |= (0x1 <<  5u);         /* Enable GPIOF clock. */ +|< 100% 5em 5em >| 
-RCC->APB2ENR |= (0x1 << 10u);         /* Enable ADC3 clock. */ +|ADCPRE|00|ADCCLK => f<sub>PCLK2</sub> / 2 (reset state)| 
- +|:::|01|ADCCLK => f<sub>PCLK2</sub> / 4| 
-/* Configure GPIO pin F.6 in analog input mode. */ +|:::|10|ADCCLK => f<sub>PCLK2</sub> / 6| 
-GPIOA->MODER |= ~(0x3 << 6u);         /* Set pin 6 to analog input mode. */ +|:::|11|ADCCLK => f<sub>PCLK2</sub> / 8|
- +
-/* No ADC common configuration, ADCCLK => PCLK2 / 2 => 21 MHz. */ +
- +
-/* Configure ADC3 channel 4. */ +
-ADC3->CR1 |= (0x3 << 24u);            /* Set resolution to 6 bit. */ +
-ADC3->SQR3 |= (4u << 0u);             /* Channel 4 first in conversion sequence (SQ1). */ +
-ADC3->SQR1 |= (0x0 << 20u);           /* Set L to 0 -> only 1 channel (SQ1) in sequence. */ +
-ADC3->CR2 |= (0x1 << 0u);             /* Enable ADC3. */ +
- +
-/* Start conversion */ +
-uint32_t data; +
-ADC3->CR2 |= (0x1 << 30u);            /* Start conversion. */ +
-while (!(ADC3->SR & (0x1 << 1u)));    /* Wait for EOC flag (end of conversion). */ +
-data = ADC3->DR; +
-</code> +
- +
-===== Configuration Registers ===== +
- +
-==== CRx ==== +
- +
-=== CR1 ===+
  
-Configuration register 1+==== ADCx_CR1 - Configuration register 1 ====
  
 \\ {{adc_reg_cr1.svg}} \\ \\ \\ {{adc_reg_cr1.svg}} \\ \\
  
 |< 100% 5em 5em >| |< 100% 5em 5em >|
-|SCAN|0|Scan mode diabled (reset state)|+|SCAN|0|Scan mode disabled (reset state)|
 |:::|1|Scan mode enabled| |:::|1|Scan mode enabled|
 |RES|00|12 bit, 15 ADCCLK cycles conversion time (reset state)| |RES|00|12 bit, 15 ADCCLK cycles conversion time (reset state)|
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 |:::|11|6 bit, 9 ADCCLK cycles conversion time| |:::|11|6 bit, 9 ADCCLK cycles conversion time|
  
-=== CR2 === +==== ADCx_CR2 - Configuration register 2 ====
- +
-Configuration register 2+
  
 \\ {{adc_reg_cr2.svg}} \\ \\ \\ {{adc_reg_cr2.svg}} \\ \\
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 |:::|1|Start conversion of regular channels||| |:::|1|Start conversion of regular channels|||
  
-==== SMPRx ==== +==== ADCx_SMPR1 - Sample time register 1 ====
- +
-=== SMPR1 === +
- +
-Sample time register 1+
  
 \\ {{adc_reg_smpr1.svg}} \\ \\ \\ {{adc_reg_smpr1.svg}} \\ \\
  
-=== SMPR2 === +==== ADCx_SMPR2 - Sample time register 2 ====
- +
-Sample time register 2+
  
 \\ {{adc_reg_smpr2.svg}} \\ \\ \\ {{adc_reg_smpr2.svg}} \\ \\
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 |:::|011|56 cycles sampling time|111|480 cycles sampling time| |:::|011|56 cycles sampling time|111|480 cycles sampling time|
  
-==== SQRx ==== +==== ADCx_SQR1 - Sequence register 1 ====
- +
-=== SQR1 === +
- +
-Sequence register 1+
  
 \\ {{adc_reg_sqr1.svg}} \\ \\ \\ {{adc_reg_sqr1.svg}} \\ \\
  
-=== SQR2 === +==== ADCx_SQR2 - Sequence register 2 ====
- +
-Sequence register 2+
  
 \\ {{adc_reg_sqr2.svg}} \\ \\ \\ {{adc_reg_sqr2.svg}} \\ \\
  
-=== SQR3 === +==== ADCx_SQR3 - Sequence register 3 ====
- +
-Sequence register 3+
  
 \\ {{adc_reg_sqr3.svg}} \\ \\ \\ {{adc_reg_sqr3.svg}} \\ \\
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 ===== Status Register ===== ===== Status Register =====
  
-==== SR ==== +==== ADCx_SR - Status register ====
- +
-Status register+
  
 \\ {{adc_reg_sr.svg}} \\ \\ \\ {{adc_reg_sr.svg}} \\ \\
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 ===== Data Register ===== ===== Data Register =====
  
-==== DR ==== +==== ADCx_DR - Data register ====
- +
-Data register+
  
 \\ {{adc_reg_dr.svg}} \\ \\ \\ {{adc_reg_dr.svg}} \\ \\
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 * Register is read only \\ \\ * Register is read only \\ \\
  
-===== Legend =====+===== Programming Example ===== 
 + 
 +<code c> 
 +#include "reg_stm32f4xx.h" 
 + 
 +RCC->AHBENR[0] |= (0x1 <<  5u);         /* Enable GPIOF clock. */ 
 +RCC->APBENR[1] |= (0x1 << 10u);         /* Enable ADC3 clock. */ 
 + 
 +/* Configure GPIO pin F.6 in analog input mode. */ 
 +GPIOA->MODER |= ~(0x3 << 6u);         /* Set pin 6 to analog input mode. */
  
-\\ {{legende.svg}} \\ \\+/* No ADC common configuration, ADCCLK => PCLK2 / 2 => 42 MHz. */
  
 +/* Configure ADC3 channel 4. */
 +ADC3->CR1 |= (0x3 << 24u);            /* Set resolution to 6 bit. */
 +ADC3->SQR3 |= (4u << 0u);             /* Channel 4 first in conversion sequence (SQ1). */
 +ADC3->SQR1 |= (0x0 << 20u);           /* Set L to 0 -> only 1 channel (SQ1) in sequence. */
 +ADC3->CR2 |= (0x1 << 0u);             /* Enable ADC3. */
 +
 +/* Start conversion */
 +uint32_t data;
 +ADC3->CR2 |= (0x1 << 30u);            /* Start conversion. */
 +while (!(ADC3->SR & (0x1 << 1u)));    /* Wait for EOC flag (end of conversion). */
 +data = ADC3->DR;
 +</code>
 +\\
  
  • stm32/peripherals/adc.1456915897.txt.gz
  • Last modified: 2016/03/02 10:51
  • by feur