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| stm32:peripherals:rtc_wakeup [2018/10/10 06:18] – [RTC_ISR] Added WUTF description kjaz | stm32:peripherals:rtc_wakeup [2021/09/06 07:29] – frtt | ||
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| |WUTF||Wake up timer flag is set by hardware when wakeup counter reaches 0 and cleared by software by writing 0.|| | |WUTF||Wake up timer flag is set by hardware when wakeup counter reaches 0 and cleared by software by writing 0.|| | ||
| * This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware. | * This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware. | ||
| + | |||
| + | ===== Back domain control register ===== | ||
| + | |||
| + | ==== RCC_BDCR ==== | ||
| + | Back domain control register | ||
| + | |||
| + | \\ {{rcc_reg_bdcr.svg}} \\ \\ | ||
| + | |||
| + | |< 100% 5em 5em >| | ||
| + | |RTCEN*|0|RTC clock disabled| | ||
| + | |:::|1|RTC clock enabled| | ||
| + | |RTCSEL|00|No clock| | ||
| + | |:::|01|LSE oscillator clock used as the RTC clock| | ||
| + | |:::|10|LSI oscillator clock used as the RTC clock| | ||
| + | |:::|11|HSE oscillator clock divided by a programmable prescaler(selection Through RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC clock| | ||
| + | |||