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Both sides previous revision Previous revision Next revision | Previous revision | ||
stm32:peripherals:rtc_wakeup [2017/08/24 13:10] – [RTC register write protection] ruan | stm32:peripherals:rtc_wakeup [2022/12/27 18:42] (current) – ruan | ||
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* Disable wakeup timer in '' | * Disable wakeup timer in '' | ||
* Wait until configuration of RTC is allowed. \\ Check corresponding bit in '' | * Wait until configuration of RTC is allowed. \\ Check corresponding bit in '' | ||
- | * Program reload value in '' | ||
* Program prescaler value in '' | * Program prescaler value in '' | ||
+ | * Program reload value in '' | ||
* Enable wakeup interrupt in '' | * Enable wakeup interrupt in '' | ||
Line 56: | Line 56: | ||
===== Configuration Registers ===== | ===== Configuration Registers ===== | ||
- | ==== RTC_CR ==== | + | ==== RTC_CR |
- | + | ||
- | Configuration register | + | |
\\ {{rtc_reg_cr.svg}} \\ \\ | \\ {{rtc_reg_cr.svg}} \\ \\ | ||
Line 72: | Line 70: | ||
|:::|1|Wake up timer interrupt enabled|| | |:::|1|Wake up timer interrupt enabled|| | ||
- | ==== RTC_WUTR ==== | + | ==== RTC_WUTR |
- | + | ||
- | Wakeup timer register | + | |
\\ {{rtc_reg_wutr.svg}} \\ \\ | \\ {{rtc_reg_wutr.svg}} \\ \\ | ||
Line 81: | Line 77: | ||
===== Status Registers ===== | ===== Status Registers ===== | ||
- | ==== RTC_ISR | + | ==== RTC_ISR |
- | + | ||
- | Initialization and status register | + | |
\\ {{rtc_reg_isr.svg}} \\ \\ | \\ {{rtc_reg_isr.svg}} \\ \\ | ||
Line 90: | Line 84: | ||
|WUTWF*|0|Wake up timer configuration not allowed| | |WUTWF*|0|Wake up timer configuration not allowed| | ||
|:::|1|Wake up timer configuration allowed| | |:::|1|Wake up timer configuration allowed| | ||
+ | |WUTF||Wake up timer flag is set by hardware when wakeup counter reaches 0 and cleared by software by writing 0.|| | ||
* This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware. | * This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware. | ||
+ | |||
+ | ===== Back domain control register ===== | ||
+ | |||
+ | ==== RCC_BDCR - Back domain control register ==== | ||
+ | |||
+ | \\ {{rcc_reg_bdcr.svg}} \\ \\ | ||
+ | |||
+ | |< 100% 5em 5em >| | ||
+ | |RTCEN*|0|RTC clock disabled| | ||
+ | |:::|1|RTC clock enabled| | ||
+ | |RTCSEL|00|No clock| | ||
+ | |:::|01|LSE oscillator clock used as the RTC clock| | ||
+ | |:::|10|LSI oscillator clock used as the RTC clock| | ||
+ | |:::|11|HSE oscillator clock divided by a programmable prescaler(selection Through RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC clock| | ||
+ |