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stm32:peripherals:rtc_wakeup [2017/08/24 13:01] – [Wake Up Timer] ruan | stm32:peripherals:rtc_wakeup [2021/09/03 08:52] – frtt: Initially Add BDCR register frtt | ||
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Line 9: | Line 9: | ||
The wakeup timer clock input can be | The wakeup timer clock input can be | ||
- | * RTCCLK (usually 32.768 kHz) divided by 2, 4, 8 or 16\\ | + | * RTCCLK (usually 32.768 kHz) divided by 2, 4, 8 or 16. \\ As a result this allows wakeup interrupt periods |
- | | + | * ck_spre (usually 1 Hz internal clock). \\ As a result this allows wakeup interrupt periods from 1 s to around 36 hours. |
===== Programming Instructions ===== | ===== Programming Instructions ===== | ||
==== RTC register write protection ==== | ==== RTC register write protection ==== | ||
- | After a reset the backup domain is write protected. \\ | + | After a reset the backup domain is write protected. The backup domain encompasses: |
Unlock access to backup domain: | Unlock access to backup domain: | ||
* Set the '' | * Set the '' | ||
Line 37: | Line 37: | ||
* Disable wakeup timer in '' | * Disable wakeup timer in '' | ||
* Wait until configuration of RTC is allowed. \\ Check corresponding bit in '' | * Wait until configuration of RTC is allowed. \\ Check corresponding bit in '' | ||
- | * Program reload value in '' | ||
* Program prescaler value in '' | * Program prescaler value in '' | ||
+ | * Program reload value in '' | ||
* Enable wakeup interrupt in '' | * Enable wakeup interrupt in '' | ||
Line 90: | Line 90: | ||
|WUTWF*|0|Wake up timer configuration not allowed| | |WUTWF*|0|Wake up timer configuration not allowed| | ||
|:::|1|Wake up timer configuration allowed| | |:::|1|Wake up timer configuration allowed| | ||
+ | |WUTF||Wake up timer flag is set by hardware when wakeup counter reaches 0 and cleared by software by writing 0.|| | ||
* This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware. | * This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware. | ||
+ | |||
+ | ===== Back domain control register ===== | ||
+ | |||
+ | ==== RCC_BDCR ==== | ||
+ | Back domain control register | ||
+ | |||
+ | \\ {{rcc_reg_bdcr.svg}} \\ \\ | ||
+ | |||
+ | |< 100% 5em 5em >| | ||
+ | |RTCEN*|0|RTC clock disabled| | ||
+ | |:::|1|RTC clock enabled| | ||
+ | |RTCSEL|00|No clock| | ||
+ | |:::|01|LSE oscillator clock used as the RTC clock| | ||
+ | |:::|10|LSI oscillator clock used as the RTC clock| | ||
+ | |:::|11|HSE oscillator clock divided by a programmable prescaler(selection Through RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC clock| | ||
+ |