Differences

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--- stm32:peripherals:rtc_wakeup [2017/08/24 12:51] – [Wake Up Timer] ruan
+++ stm32:peripherals:rtc_wakeup [2021/09/06 07:29] – frtt
@@ Line 6: / Line 6: @@
 \\ {{rtc_timer.svg?700em}} \\ \\
-The wakeup timer can be used to generate a periodic interrupt through the wakeup timer flag (WUTF). Additionally the WUTF flag can be output (through signals RTC_ALARM and RTC_AF1) to pin PC13.
+The wakeup timer can be used to generate a periodic interrupt through the wakeup timer flag (WUTF). Additionally the WUTF flag can be output (through signals WKUP, RTC_ALARM and on to RTC_AF1) to pin PC13.
+The wakeup timer clock input can be
+  * RTCCLK (usually 32.768 kHz) divided by 2, 4, 8 or 16. \\ As a result this allows wakeup interrupt periods from 122 us to 32 s, with a resolution down to 61 us.
+  * ck_spre (usually 1 Hz internal clock). \\ As a result this allows wakeup interrupt periods from 1 s to around 36 hours.
 ===== Programming Instructions =====
 ==== RTC register write protection ====
-After a reset the backup domain is write protected. \\
+After a reset the backup domain is write protected. The backup domain encompasses: RTC, LSE oscillator, backup SRAM, I/O pins PC13 to PC15 and PI8. The backup domain is powered through VBAT even if VDD is turned off.\\
 Unlock access to backup domain:
   * Set the ''DBP'' bit (disable backup protection) in ''PWR->CR''.
@@ Line 33: / Line 37: @@
   * Disable wakeup timer in ''RTC->CR''.
   * Wait until configuration of RTC is allowed. \\ Check corresponding bit in ''RTC->ISR''.
-  * Program reload value in ''RTC->WUTR''.
   * Program prescaler value in ''RTC->CR''.
+  * Program reload value in ''RTC->WUTR''.
   * Enable wakeup interrupt in ''RTC->CR''.
@@ Line 86: / Line 90: @@
 |WUTWF*|0|Wake up timer configuration not allowed|
 |:::|1|Wake up timer configuration allowed|
+|WUTF||Wake up timer flag is set by hardware when wakeup counter reaches 0 and cleared by software by writing 0.||
 * This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware.
+===== Back domain control register =====
+==== RCC_BDCR ====
+Back domain control register
+\\ {{rcc_reg_bdcr.svg}} \\ \\
+|< 100% 5em 5em >|
+|RTCEN*|0|RTC clock disabled|
+|:::|1|RTC clock enabled|
+|RTCSEL|00|No clock|
+|:::|01|LSE oscillator clock used as the RTC clock|
+|:::|10|LSI oscillator clock used as the RTC clock|
+|:::|11|HSE oscillator clock divided by a programmable prescaler(selection Through RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC clock|